Patents Examined by Monica D. Harrison
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Patent number: 11610981Abstract: A method for manufacturing a semiconductor device comprising: providing a substrate, wherein an amorphous silicon layer is formed on the substrate; forming an etching auxiliary layer on the amorphous silicon layer, wherein the upper surface of the etching auxiliary layer is flat, and the etching auxiliary layer is made of a single material; and etching the amorphous silicon layer and the etching auxiliary layer to obtain an amorphous silicon layer with a target thickness, wherein the upper surface of the etched amorphous silicon layer is flat.Type: GrantFiled: April 7, 2021Date of Patent: March 21, 2023Assignee: Shanghai Huali Integrated Circuit CorporationInventors: Changhung Kung, Xiantao Li, Xiumei Hu, Jianxun Chen, Chanyuan Hu
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Patent number: 11610774Abstract: Methods for forming a topographically selective silicon oxide film by a cyclical plasma-enhanced deposition process are provided. The methods may include: forming a topographically selective silicon oxide film by a plasma enhanced atomic layer deposition (PEALD) process or a cyclical plasma-enhanced chemical vapor deposition (cyclical PECVD) process. The methods may also include: forming a silicon oxide film either selectivity over the horizontal surfaces of a non-planar substrate or selectively over the vertical surfaces of a non-planar substrate.Type: GrantFiled: September 29, 2020Date of Patent: March 21, 2023Assignee: ASM IP Holding B.V.Inventors: Aurélie Kuroda, Atsuki Fukazawa
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Patent number: 11610979Abstract: A method includes etching a silicon layer in a wafer to form a first trench in a first device region and a second trench in a second device region, performing a pre-clean process on the silicon layer, performing a baking process on the wafer, and performing an epitaxy process to form a first silicon germanium region and a second silicon germanium region in the first trench and the second trench, respectively. The first silicon germanium region and the second silicon germanium region have a loading in a range between about 5 nm and about 30 nm.Type: GrantFiled: January 13, 2021Date of Patent: March 21, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventor: Shahaji B. More
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Patent number: 11610889Abstract: Techniques are disclosed for providing an integrated circuit structure having NMOS transistors including an arsenic-doped interface layer between epitaxially grown source/drain regions and a channel region. The arsenic-doped interface layer may include, for example, arsenic-doped silicon (Si:As) having arsenic concentrations in a range of about 1E20 atoms per cm3 to about 5E21 atoms per cm3. The interface layer may have a relatively uniform thickness in a range of about 0.5 nm to full fill where the entire source/drain region is composed of the Si:As. In cases where the arsenic-doped interface layer only partially fills the source/drain regions, another n-type doped semiconductor material can fill remainder (e.g., phosphorus-doped III-V compound or silicon).Type: GrantFiled: September 28, 2018Date of Patent: March 21, 2023Assignee: Intel CorporationInventors: Anand Murthy, Ryan Keech, Nicholas G. Minutillo, Ritesh Jhaveri
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Patent number: 11610982Abstract: A method of forming a semiconductor device includes: forming a dummy gate over a fin, where the fin protrudes above a substrate; surrounding the dummy gate with a dielectric material; and replacing the dummy gate with a replacement gate structure, where replacing the dummy gate includes: forming a gate trench in the dielectric material, where forming the gate trench includes removing the dummy gate; forming a metal-gate stack in the gate trench, where forming the metal-gate stack includes forming a gate dielectric layer, a first work function layer, and a gap-filling material sequentially in the gate trench; and enlarging a volume of the gap-filling material in the gate trench.Type: GrantFiled: January 4, 2021Date of Patent: March 21, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chih-Hsiang Fan, Tsung-Han Shen, Jia-Ming Lin, Wei-Chin Lee, Hsien-Ming Lee, Chi On Chui
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Patent number: 11600642Abstract: Embodiments of the present disclosure generally relate to a layer stack including a high K dielectric layer formed over a first dielectric layer and a metal electrode. The high K dielectric layer has a K value of 20 or higher and may be formed as a part of a capacitor, a gate insulating layer, or any suitable insulating layer in electronic devices, such as display devices. The layer stack includes a second dielectric layer disposed on the first dielectric layer and the metal layer, and the high K dielectric layer containing zirconium dioxide or hafnium dioxide disposed on the second dielectric layer. The second dielectric layer provides a homogenous surface on which the high K dielectric layer is formed. The homogeneous surface enables the high K dielectric material to be deposited uniformly thereover, resulting in a uniform thickness profile.Type: GrantFiled: May 27, 2021Date of Patent: March 7, 2023Assignee: APPLIED MATERIALS, INC.Inventors: Xiangxin Rui, Soo Young Choi, Shinichi Kurita, Yujia Zhai, Lai Zhao
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Patent number: 11600717Abstract: A method includes forming isolation regions extending into a semiconductor substrate, wherein semiconductor strips are located between the isolation regions, and forming a dielectric dummy strip between the isolation regions, recessing the isolation regions. Some portions of the semiconductor strips protrude higher than top surfaces of the recessed isolation regions to form protruding semiconductor fins, and a portion of the dielectric dummy strip protrudes higher than the top surfaces of the recessed isolation regions to form a dielectric dummy fin. The method further includes etching the dielectric dummy fin so that a top width of the dielectric dummy fin is smaller than a bottom width of the dielectric dummy fin. A gate stack is formed on top surfaces and sidewalls of the protruding semiconductor fins and the dielectric dummy fin.Type: GrantFiled: October 13, 2020Date of Patent: March 7, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTDInventors: Shih-Yao Lin, Pei-Hsiu Wu, Chih Ping Wang, Chih-Han Lin, Jr-Jung Lin, Yun Ting Chou, Chen-Yu Wu
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Patent number: 11600567Abstract: A semiconductor device package includes a first circuit layer, a second circuit layer, a first semiconductor die and a second semiconductor die. The first circuit layer includes a first surface and a second surface opposite to the first surface. The second circuit layer is disposed on the first surface of the first circuit layer. The first semiconductor die is disposed on the first circuit layer and the second circuit layer, and electrically connected to the first circuit layer and the second circuit layer. The second semiconductor die is disposed on the second circuit layer, and electrically connected to the second circuit layer.Type: GrantFiled: July 31, 2019Date of Patent: March 7, 2023Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: Chih-Cheng Lee, Kuang Hsiung Chen
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Patent number: 11600718Abstract: A semiconductor device and method of fabricating a semiconductor device involves formation of a trench above a fin (e.g. a fin of a FinFET device) of the semiconductor device and formation of a multi-layer dielectric structure within the trench. The profile of the multi-layer dielectric structure can be controlled depending on the application to reduce shadowing effects and reduce cut failure risk, among other possible benefits. The multi-layer dielectric structure can include two layers, three layers, or any number of layers and can have a stepped profile, a linear profile, or any other type of profile.Type: GrantFiled: April 22, 2021Date of Patent: March 7, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITEDInventors: Ya-Yi Tsai, Chi-Hsiang Chang, Shih-Yao Lin, Tzu-Chung Wang, Shu-Yuan Ku
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Patent number: 11594634Abstract: A FinFET device structure and method for forming the same are provided. The FinFET device structure includes a stop layer formed over a substrate and a fin structure formed over the stop layer. The FinFET device structure includes a gate structure formed over the fin structure and a source/drain (S/D) structure adjacent to the gate structure. A bottom surface of the S/D structure is located at a position that is higher than or level with a bottom surface of the stop layer.Type: GrantFiled: August 28, 2020Date of Patent: February 28, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Che-Cheng Chang, Chih-Han Lin
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Patent number: 11594423Abstract: The present disclosure provides a method of forming a capacitor array and a semiconductor structure. The method of forming a capacitor array includes: providing a substrate, the substrate including an array region and a non-array region, wherein a base layer and a dielectric layer are formed in the substrate, and a first barrier layer is formed between the base layer and the dielectric layer; forming, on a surface of the dielectric layer, a first array definition layer and a second array definition layer respectively corresponding to the array region and the non-array region; forming a pattern transfer layer on a surface of each of the first array definition layer and the second array definition layer; patterning the dielectric layer and the second array definition layer by using the pattern transfer layer as a mask, and forming a capacitor array located in the array region.Type: GrantFiled: January 17, 2022Date of Patent: February 28, 2023Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.Inventor: Qiang Wan
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Patent number: 11594577Abstract: A color filter is disposed on a substrate. An organic photodiode is disposed on the color filter. The organic photodiode includes an electrode insulating layer having a recess region on the substrate, a first electrode on the color filter, the first electrode filling the recess region of the electrode insulating layer, a second electrode on the first electrode, and an organic photoelectric conversion layer interposed between the first electrode and the second electrode. The first electrode includes a seam extending at a first angle from a side surface of the recess region of the electrode insulating layer.Type: GrantFiled: November 5, 2021Date of Patent: February 28, 2023Inventors: Gwi-Deok Ryan Lee, Jung Hun Kim, Chang Hwa Kim, Sang Su Park, Sang Hoon Uhm, Beom Suk Lee, Tae Yon Lee, Dong Mo Im
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Patent number: 11587928Abstract: Methods and structures for forming strained-channel finFETs are described. Fin structures for finFETs may be formed using two epitaxial layers of different lattice constants that are grown over a bulk substrate. A first thin, strained, epitaxial layer may be cut to form strain-relieved base structures for fins. The base structures may be constrained in a strained-relieved state. Fin structures may be epitaxially grown in a second layer over the base structures. The constrained base structures can cause higher amounts of strain to form in the epitaxially-grown fins than would occur for non-constrained base structures.Type: GrantFiled: November 9, 2020Date of Patent: February 21, 2023Assignee: Bell Semiconductor, LLCInventors: Pierre Morin, Nicolas Loubet
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Patent number: 11588026Abstract: A method for fabricating a semiconductor device includes forming a stack structure including a horizontal recess over a substrate, forming a blocking layer lining the horizontal recess, forming an interface control layer including a dielectric barrier element and a conductive barrier element over the blocking layer, and forming a conductive layer over the interface control layer to fill the horizontal recess.Type: GrantFiled: January 13, 2020Date of Patent: February 21, 2023Assignee: SK hynix Inc.Inventors: Hyeng-Woo Eom, Jung-Myoung Shim, Young-Ho Yang, Kwang-Wook Lee, Won-Joon Choi
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Patent number: 11581306Abstract: A method of manufacture and structure for a monolithic single chip single crystal device. The method can include forming a first single crystal epitaxial layer overlying the substrate and forming one or more second single crystal epitaxial layers overlying the first single crystal epitaxial layer. The first single crystal epitaxial layer and the one or more second single crystal epitaxial layers can be processed to form one or more active or passive device components. Through this process, the resulting device includes a monolithic epitaxial stack integrating multiple circuit functions.Type: GrantFiled: February 19, 2021Date of Patent: February 14, 2023Assignee: Akoustis, Inc.Inventors: Shawn R. Gibb, David Aichele, Ramakrishna Vetury, Mark D. Boomgarden, Jeffrey B. Shealy
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Patent number: 11581402Abstract: A method and apparatus include an n-doped layer having a first applied charge, and a p?-doped layer having a second applied charge. The p?-doped layer may be positioned below the n-doped layer. A p+-doped buffer layer may have a third applied charge and be positioned below the p?-doped layer. The respective charges at each layer may be determined based on a dopant level and a physical dimension of the layer. In one example, the n-doped layer, the p?-doped layer, and the p+-doped buffer layer comprise a lateral semiconductor manufactured from silicon carbide (SiC).Type: GrantFiled: September 5, 2019Date of Patent: February 14, 2023Assignee: Board of Regents, The University of Texas SystemInventor: Qin Huang
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Patent number: 11581313Abstract: Disclosed herein are IC structures, packages, and devices that include III-N transistors integrated on the same support structure as non-III-N transistors (e.g., Si-based transistors), using semiconductor regrowth. In one aspect, a non-III-N transistor may be integrated with an III-N transistor by depositing a III-N material, forming an opening in the III-N material, and epitaxially growing within the opening a semiconductor material other than the III-N material. Since the III-N material may serve as a foundation for forming III-N transistors, while the non-III-N material may serve as a foundation for forming non-III-N transistors, such an approach advantageously enables implementation of both types of transistors on a single support structure. Proposed integration may reduce costs and improve performance by enabling integrated digital logic solutions for III-N transistors and by reducing losses incurred when power is routed off chip in a multi-chip package.Type: GrantFiled: February 22, 2019Date of Patent: February 14, 2023Assignee: Intel CorporationInventors: Sansaptak Dasgupta, Johann Christian Rode, Han Wui Then, Marko Radosavljevic, Paul B. Fischer, Nidhi Nidhi, Rahul Ramaswamy, Sandrine Charue-Bakker, Walid M. Hafez
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Patent number: 11581288Abstract: The present disclosure relates to a radio frequency device that includes a transfer device die and a multilayer redistribution structure underneath the transfer device die. The transfer device die includes a device region with a back-end-of-line (BEOL) portion and a front-end-of-line (FEOL) portion over the BEOL portion and a transfer substrate. The FEOL portion includes isolation sections and an active layer surrounded by the isolation sections. A top surface of the device region is planarized. The transfer substrate including a porous silicon (PSi) region resides over the top surface of the device region. Herein, the PSi region has a porosity between 1% and 80%. The multilayer redistribution structure includes a number of bump structures, which are at a bottom of the multilayer redistribution structure and electrically coupled to the FEOL portion of the transfer device die.Type: GrantFiled: November 8, 2019Date of Patent: February 14, 2023Assignee: Qorvo US, Inc.Inventors: Julio C. Costa, Michael Carroll
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Patent number: 11581253Abstract: A semiconductor device including an interlayer insulating layer on a substrate; a conductive line on the interlayer insulating layer; and a contact plug penetrating the interlayer insulating layer, the contact plug being connected to the conductive line, wherein the contact plug includes an upper pattern penetrating an upper region of the interlayer insulating layer, the upper pattern protruding upwardly from a top surface of the interlayer insulating layer, the upper pattern includes a first portion penetrating the upper region of the interlayer insulating layer; and a second portion protruding upwardly from the top surface of the interlayer insulating layer, and a width of a lower region of the second portion in a direction parallel to a top surface of the substrate is greater than a width of an upper region of the second portion in the direction parallel to the top surface of the substrate.Type: GrantFiled: October 18, 2021Date of Patent: February 14, 2023Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Donghee Seo, Heonbok Lee, Tae-Yeol Kim, Daeyong Kim, Dohyun Lee
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Patent number: 11581474Abstract: Techniques for forming quantum circuits, including connections between components of quantum circuits, are presented. A trench can be formed in a dielectric material, by removing a portion of the dielectric material and a portion of conductive material layered on top of the dielectric material, to enable creation of circuit components of a circuit. The trench can define a regular nub or compensated nub to facilitate creating electrical leads connected to the circuit components on a nub. The compensated nub can comprise recessed regions to facilitate depositing material during evaporation to form the leads. For compensated nub implementation, material can be evaporated in two directions, with oxidation performed in between such evaporations, to contact leads and form a Josephson junction. For regular nub implementation, material can be evaporated in four directions, with oxidation performed in between the third and fourth evaporations, to contact leads and form a Josephson junction.Type: GrantFiled: December 28, 2020Date of Patent: February 14, 2023Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Vivekananda P. Adiga, Martin O. Sandberg, Jerry M. Chow