Abstract: An AC to DC converter system is disclosed in which a conversion circuit for converting an AC input signal to a DC output signal is operably coupled with a communication circuit designed for sensing output indicative of the presence or absence of a load at the DC output. The system is designed so that the conversion circuit operates in an inactive standby state when there is no load, and in an active state for supplying DC power when a load is present. The system is configured to operate using ultra-low power.

Abstract: A power conversion system eliminates output transformers and replaces them with a zig-zag transformer and a filter that provides a 3-phase 5-wire system with significantly reduced weight and size as compared with conventional systems. The zig-zag transformer may have a low zero sequence impedance. The power conversion system also ensures operational safety by detecting various types of ground faults.

Abstract: A cascaded electric power converter and a method of operating a cascaded electric power converter are disclosed. The cascaded converter includes: a converter cell including a cell capacitor and at least one phase leg having at least two electric valves, the at least one phase leg being connected in parallel to the cell capacitor; and a control system for controlling the switching of the electric valves of the at least one phase leg. The control system is configured to, upon detection of a need to by-pass the converter cell, control the switching of the electric valves in a manner so that the cell capacitor is short circuited via a phase leg, so as to obtain a current surge through the phase leg, thereby creating a permanent current path through the converter cell.

Abstract: A power source apparatus includes: a first alternating current line; a second alternating current line; an electric power inputting portion including a rectifying circuit for rectifying an alternating current voltage supplied from an alternating current power source, the electric power inputting portion serving to output the rectified voltage to each of the first and second alternating current lines; a first converter including a switching element for converting the alternating current voltage into a first direct current voltage; a second converter for converting the first direct current voltage obtained in the first converter into a second direct current voltage; and a control circuit for carrying out control for driving at least the switching element of the first converter so as to be turned ON or OFF.

Abstract: An efficiency measuring circuit may measure the efficiency of a DC-DC converter having a switching inductor with an internal DC resistance and a plurality of electronic switches that control current through the inductor. A duty cycle circuit may measure the duty cycle of current flowing through one of the electronic switches. A current sense circuit may measure the current flowing through one of the electronic switches. An inductor voltage sensor circuit may measure the voltage across the inductor. A computation circuit may compute the internal DC resistance of the switching inductor based in part on the duty cycle measured by the duty cycle circuit and the current measured by the current sense circuit. The computation circuit may also compute the efficiency of the DC-DC converter.

Abstract: Switch-mode power conversion system and method thereof. The switch-mode power conversion system includes a primary winding configured to receive an input voltage, and a secondary winding coupled to the primary winding and configured to, with one or more other components, generate an output signal. Additionally, the switch-mode power conversion system includes a feedback component configured to receive the output signal and generate a feedback signal based on at least information associated with the output signal, and a voltage detector configured to receive the input voltage and output a detection signal. Moreover, the switch-mode power conversion system includes a mode controller configured to receive the detection signal and the feedback signal and generate a switch signal based on at least information associated with the detection signal and the feedback signal, and a switch configured to receive the switch signal and affect a first current flowing through the primary winding.

Abstract: In one embodiment, a switching mode power supply (SMPS) includes a rectifier for generating an input DC voltage from an input AC voltage. A switching transistor, coupled to a primary coil of a transformer, converts the input DC voltage and supplies power to a secondary side of the transformer according to an operation of the switching transistor. A switching controller receives a feedback voltage corresponding to a voltage of the secondary side of the transformer, a sense signal corresponding to current flowing at the switching transistor, and a first signal corresponding to a voltage difference between first and second electrodes of the switching transistor. The switching controller controls the turning on and off of the switching transistor. After the switching transistor is turned off, the switching controller detects and counts a number of times that a voltage level of the first signal and a reference voltage are equal.

Abstract: Integrated circuit devices include a semiconductor substrate and a flux line generating passive electronic element on the semiconductor substrate. A dummy gate structure is arranged on the semiconductor substrate in a region below the passive electronic element. The dummy gate includes a plurality of segments, each segment including a first longitudinally extending part and a second longitudinally extending part. The second longitudinally extending part extends at an angle from an end of the first longitudinally extending part. Ones of the segments extend at a substantially same angle and are arranged displaced from each other in an adjacent nested relationship.

Abstract: A semiconductor device assembly and method of making the device are disclosed. The assembly comprises a semiconductor die attached to an electrically conductive layer, which is, in turn, connected to a dielectric layer carrying conductive traces of an electrical connection layer. The conductive traces provide connection between an array of discrete conductive elements and bonding wires connected to bond pads of the die. The conductive layer enhances thermal conduction and structural stiffness for the assembly. In addition, the conductive layer provides a voltage reference plane that may be connected to a power source, a ground source, or an intermediate reference voltage. The conductive layer also includes at least one electrical current isolation slot, which segments the conductive layer to help isolate noise induced in one segment of the conductive layer from the other segments.

Abstract: A stacked semiconductor package comprises two semiconductor chips (11, 12) each of which has a mounting surface provided with a plurality of chip pins arranged in a predetermined pattern. The semiconductor chips are mounted on opposite surfaces of a substrate (13) so that the mounting surfaces are faced to each other through the substrate. The substrate is provided with a plurality of package pins formed in an area other than a chip mounting area and arranged in a pattern identical to the predetermined pattern. A pair of the corresponding chip pins of the semiconductor chips are connected to a via formed at an intermediate position therebetween by the use of branch wires equal in length to each other. The via is connected by a common wire to the package pin corresponding to the chip pins connected to the via.

Abstract: A method of fabricating an apparatus including a sealed cavity and an apparatus embodying the method are disclosed. To fabricate the apparatus, a device chip including a substrate and at least one circuit element on the substrate is fabricated. Also, a cap is fabricated. Next, the device chip and the cap are bonded such that a sealed cavity is formed by the device chip and the cap. The bond is accomplished using thermo compression technique. Gold or other suitable metal can be used as a bonding agent. Then or at the same time, caulking agent is reflowed over the bonding agent, over portions of the cap, or both to further seal the cavity. In the resultant device, the sealed cavity is sealed by the bonding agent, the caulking agent, or both. The caulking agent increases hermeticity of the cavity and provides for even higher level of protection of the cavity against adverse environmental conditions.

Abstract: A package structure and fabrication method thereof. The structure includes a substrate having a terminal, a chip overlying the substrate, the chip having an active surface, having a center region and periphery region, the periphery region having an electrode thereon, a patterned cover plate overlying the chip and exposing the electrode, a conductive material electrically connecting the electrode and terminal, and an encapsulant covering the terminal, conductive material, and electrode, but exposing the cover plate overlying the center region of the chip.

Abstract: A semiconductor device with a substrate, a first electrode on the substrate, at least one of an injection layer or a transporting layer on the first electrode, an adhesion layer on the at least one of an injection layer or a transporting layer, and a second electrode on the adhesion layer.

Abstract: In one aspect, the invention includes a semiconductor processing method. An antireflective material layer is formed over a substrate. At least a portion of the antireflective material layer is annealed at a temperature of greater than about 400° C. A layer of photoresist is formed over the annealed antireflective material layer. The layer of photoresist is patterned. A portion of the antireflective material layer unmasked by the patterned layer of photoresist is removed. In another aspect, the invention includes the following semiconductor processing. An antireflective material layer is formed over a substrate. The antireflective material layer is annealed at a temperature of greater than about 400° C. A layer of photoresist is formed over the annealed antireflective material layer. Portions of the layer of photoresist are exposed to radiation waves. Some of the radiation waves are absorbed by the antireflective material during the exposing.

Abstract: Disclosed are semiconductor devices containing a polymer dielectric and at least one active device containing an organic semiconductor material and a passive layer. Also disclosed are semiconductor devices further containing a conductive polymer. Such devices are characterized by light weight and robust reliability.

Abstract: Method and apparatus for integrating capacitors in stacked integrated circuits are described. One aspect of the invention relates to a semiconductor assembly having a carrier substrate, a plurality of integrated circuit dice, and at least one metal-insulator-metal (MIM) capacitor. The integrated circuit dice are vertically stacked on the carrier substrate. Each MIM capacitor is disposed between a first integrated circuit die and a second integrated circuit die of the plurality of integrated circuit dice. The at least one MIM capacitor is fabricated on at least one of a face of the first integrated circuit die and a backside of the second integrated circuit die.

Abstract: The present invention provides a method of making a stackable power semiconductor package system comprising forming a lower lead frame, having an upward bent source lead and an upward bent gate lead, mounting a power semiconductor device on the lower lead frame utilizing interconnect structures and forming an upper lead frame wherein the upper lead frame is on the power semiconductor device.

Abstract: A microelectronic package comprises a chip stack (110) that includes a substrate (111), a first die (112) over the substrate and a second die (113) over the first die, a first underfill layer (114) between the substrate and the first die, and a second underfill layer (115) between the first die and the second die. The microelectronic package further comprises a fluidic microchannel system (120) in the chip stack, and the fluidic microchannel system comprises a fluid inlet (121) and a fluid outlet (122) connected to each other by a fluidic passage (123).

Abstract: A light emitting diode including a substrate, a semiconductor layer, multiple electrodes, a passivation layer, multiple under bump metallurgy (UBM) layers and a reflective layer is provided. The semiconductor layer is disposed on the substrate. The electrodes and the passivation layer are disposed on the semiconductor layer. The passivation layer has multiple openings for exposing the electrodes. The UBM layers are disposed on the electrodes. The reflective layer is disposed on the passivation layer. The reflective layer is electrically isolated from the electrodes and the UBM layers. A method of fabricating the light emitting diode is also provided. The reflective layer and the UBM layers are fabricated simultaneously in one process. Therefore, the fabricating method is compatible with the existing process.

Abstract: To realize a high-performance liquid crystal display device or light-emitting element using a plastic film. A CPU is formed over a first glass substrate and then, separated from the first substrate. A pixel portion having a light-emitting element is formed over a second glass substrate, and then, separated from the second substrate. The both are bonded to each other. Therefore, high integration can be achieved. Further, in this case, the separated layer including the CPU serves also as a sealing layer of the light-emitting element.