Patents Examined by Mouloucoulaye Inoussa
  • Patent number: 11569255
    Abstract: Electronic apparatus and methods of forming the electronic apparatus may include one or more charge trap structures for use in a variety of electronic systems and devices, where each charge trap structure includes a dielectric barrier between a gate and a blocking dielectric on a charge trap region of the charge trap structure. In various embodiments, a void is located between the charge trap region and a region on which the charge trap structure is disposed. In various embodiments, a tunnel region separating a charge trap region from a semiconductor pillar of a charge trap structure, can be arranged such that the tunnel region and the semiconductor pillar are boundaries of a void. Additional apparatus, systems, and methods are disclosed.
    Type: Grant
    Filed: May 7, 2021
    Date of Patent: January 31, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Chris M. Carlson, Ugo Russo
  • Patent number: 11569096
    Abstract: An semiconductor device includes a first dielectric layer, an etch stop layer, an interconnect structure, and a second dielectric layer. The etch stop layer is over the first dielectric layer. The interconnect structure includes a conductive via in the first dielectric layer and the etch stop layer, a conductive line over the conductive via, an intermediate conductive layer over the conductive line, and a conductive pillar over the intermediate conductive layer. The interconnect structure is electrically conductive at least from a top of the conductive pillar to a bottom of the conductive via. The second dielectric layer surrounds the conductive line, the intermediate conductive layer, and the conductive pillar, wherein a bottom of the second dielectric layer is lower than a top of the conductive line, and a top of the second dielectric layer is higher than the top of the conductive line.
    Type: Grant
    Filed: May 21, 2021
    Date of Patent: January 31, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Hsi-Wen Tien, Wei-Hao Liao, Chih-Wei Lu, Pin-Ren Dai, Chung-Ju Lee
  • Patent number: 11555924
    Abstract: A handheld laser distance measuring device for a contactless distance measurement between the laser distance measuring device and a remote object uses a laser beam that is emitted by the laser distance measuring device. The laser distance measuring device includes a device-side coupling device paired with the device housing. The coupling device is configured for reversibly arranging at least one attachment device on the laser distance measuring device. By arranging the at least one attachment device on the laser distance measuring device, at least one additional functionality can be provided.
    Type: Grant
    Filed: October 5, 2017
    Date of Patent: January 17, 2023
    Assignee: Robert Bosch GmbH
    Inventors: Stephan Thiemt, Hendrik Hesse, Volkan Akbiyik, Markus Lassmann, Lena Popiolek, Joerg Stierle, Corinna Sorg, Felix Gärtner
  • Patent number: 11557650
    Abstract: A semiconductor device including a FET includes an isolation insulating layer disposed in a trench of the substrate, a gate dielectric layer disposed over a channel region of the substrate, a gate electrode disposed over the gate dielectric layer, a source and a drain disposed adjacent to the channel region, and an embedded insulating layer disposed below the source, the drain and the gate electrode and both ends of the embedded insulating layer are connected to the isolation insulating layer.
    Type: Grant
    Filed: April 23, 2020
    Date of Patent: January 17, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chun Hsiung Tsai, Chih-Hsin Ko, Clement Hsing Jen Wann, Ya-Yun Cheng
  • Patent number: 11552155
    Abstract: A method for manufacturing a display device includes providing an electronic component between a plurality of bumps, providing a display panel, aligning the electronic component and the display panel, and applying ultrasonic waves to bond the plurality of bumps to signal pads. In providing first adhesive members, at least a portion of a top surface of each of the plurality of bumps is exposed between the first adhesive members.
    Type: Grant
    Filed: July 31, 2020
    Date of Patent: January 10, 2023
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Chan-Jae Park, Sangduk Lee, Heeju Woo, Kikyung Youk, Hyun a Lee, Daehwan Jang
  • Patent number: 11545602
    Abstract: The display panel includes: a panel cover; an adhesive layer positioned below the panel cover; and a plurality of display modules detachably attached to the panel cover by the adhesive layer. The adhesive layer includes: a first adhesive layer positioned on the plurality of display modules, and a second adhesive layer positioned on the first adhesive layer. A peel strength of the second adhesive layer is greater than a peel strength of the first adhesive layer.
    Type: Grant
    Filed: July 22, 2020
    Date of Patent: January 3, 2023
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Pil Yong Oh, Kwang Jae Lee, Sung Soo Jung, Jeong In Han
  • Patent number: 11538734
    Abstract: A power semiconductor module includes a substrate with a metallization layer and a power semiconductor chip bonded to the metallization layer of the substrate. A metallic plate has a first surface bonded to a surface of the power semiconductor chip opposite to the substrate. The metallic plate has a central part and a border that are both bonded to the power semiconductor chip. The border of the metallic plate is structured in such a way that the metallic plate has less metal material per volume at the border as compared to the central part of the metallic plate. Metallic interconnection elements are bonded to a second surface of the metallic plate at the central part.
    Type: Grant
    Filed: April 8, 2019
    Date of Patent: December 27, 2022
    Assignee: Hitachi Energy Switzerland AG
    Inventors: Fabian Mohn, Alexey Sokolov, Chunlei Liu
  • Patent number: 11532619
    Abstract: Transistor structures including a non-planar body that has an active portion comprising a semiconductor material of a first height that is variable, and an inactive portion comprising an oxide of the semiconductor material of a second variable height, complementary to the first height. Gate electrodes and source/drain terminals may be coupled through a transistor channel having any width that varies according to the first height. Oxidation of a semiconductor material may be selectively catalyzed to convert a desired portion of a non-planar body into the oxide of the semiconductor material. Oxidation may be enhanced through the application of a catalyst, such as one comprising metal and oxygen, for example.
    Type: Grant
    Filed: March 27, 2019
    Date of Patent: December 20, 2022
    Assignee: Intel Corporation
    Inventors: Willy Rachmady, Cheng-Ying Huang, Gilbert Dewey, Jack Kavalieros, Caleb Barrett, Jay P. Gupta, Nishant Gupta, Kaiwen Hsu, Byungki Jung, Aravind S. Killampalli, Justin Railsback, Supanee Sukrittanon, Prashant Wadhwa
  • Patent number: 11527431
    Abstract: According to an aspect of the disclosed technology, there is provided a method comprising: providing a substrate, the substrate supporting an STI-layer and a set of fin structures, each fin structure comprising an upper portion protruding above the STI-layer, forming a spacer layer over the upper portions of the set of fin structures and the STI-layer, forming a sacrificial layer over the spacer layer, the sacrificial layer at least partially embedding the upper portions of the fin structures, partially etching back the sacrificial layer to expose spacer layer portions above upper surfaces of the upper portions of the set of fin structures, and etching the spacer layer and exposing at least the upper surfaces of the upper portions of the set of fin structures, while the sacrificial layer at least partially masks spacer layer portions above the STI-layer.
    Type: Grant
    Filed: December 11, 2020
    Date of Patent: December 13, 2022
    Assignee: IMEC vzw
    Inventors: Boon Teik Chan, Efrain Altamirano Sanchez, Geert Mannaert
  • Patent number: 11527550
    Abstract: A memory array comprises a vertical stack comprising alternating insulative tiers and wordline tiers. The wordline tiers comprise gate regions of individual memory cells. The gate regions individually comprise part of a wordline in individual of the wordline tiers. Channel material extends elevationally through the insulative tiers and the wordline tiers. The individual memory cells comprise a memory structure laterally between the gate region and the channel material. Individual of the wordlines comprise opposing laterally-outer longitudinal edges. The longitudinal edges individually comprise a longitudinally-elongated recess extending laterally into the respective individual wordline. Methods are disclosed.
    Type: Grant
    Filed: February 17, 2021
    Date of Patent: December 13, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Changhan Kim, Richard J. Hill, John D. Hopkins, Collin Howder
  • Patent number: 11521070
    Abstract: There is provided an information processing device which efficiently executes machine learning. The information processing device according to one embodiment includes: an obtaining unit which obtains a source code including a code which defines Forward processing of each layer constituting a neural network; a storage unit which stores an association relationship between each Forward processing and Backward processing associated with each Forward processing; and an executing unit which successively executes each code included in the source code, and which calculates an output value of the Forward processing defined by the code based on an input value at a time of execution of each code, and generates a reference structure for Backward processing in a layer associated with the code based on the association relationship stored in the storage unit.
    Type: Grant
    Filed: September 2, 2016
    Date of Patent: December 6, 2022
    Assignee: Preferred Networks, Inc.
    Inventors: Seiya Tokui, Yuya Unno, Kenta Oono, Ryosuke Okuta
  • Patent number: 11522032
    Abstract: A display device according to an exemplary embodiment of the present invention includes: a first substrate and a second substrate; a plurality of signal lines that are formed on the first substrate or on the second substrate; and a plurality of side wires that are disposed in a side surface of a first edge of the first substrate and a side surface of a second edge of the second substrate, wherein the plurality of side wires are disposed apart from each other along a direction in which the first edge extends, and are connected with the plurality of signal lines, and a first thickness of side wires disposed at an end of the first edge and at and end of the second edge is different from a second thickness of the side wire disposed at inside of the edges of live first edge and the second edge.
    Type: Grant
    Filed: December 30, 2019
    Date of Patent: December 6, 2022
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventor: Young-Cheol Jeong
  • Patent number: 11513775
    Abstract: In a method of group control and management among electronic devices, wherein the electronic devices is in communication with a control device, a projectable space instance is provided for the control device to create a workspace, wherein a control and management tool and a plurality of unified tools for driving respective electronic devices are selectively added to the projectable space instance. The projectable space instance is then parsed with a projector by the control device to automatically generate a projected workspace corresponding to the workspace to be created via the projectable space instance. The control and management tool realizes at least one status information of at least a first one of the electronic devices by way of the unified tools, and controls at least a second one of the electronic devices to execute at least one task corresponding to the at least one status information.
    Type: Grant
    Filed: June 26, 2015
    Date of Patent: November 29, 2022
    Assignee: Able World International Limited
    Inventors: Wai-Tung Cheung, Chun-Hsiao Lin, Shih-Cheng Lan, Ho-Cheung Cheung
  • Patent number: 11508884
    Abstract: The invention relates to a method for producing a plurality of optoelectronic semiconductor components, including the following steps: preparing a plurality of semiconductor chips spaced in a lateral direction to one another; forming a housing body assembly, at least one region of which is arranged between the semiconductor chips; forming a plurality of fillets, each adjoining a semiconductor chip and being bordered in a lateral direction by a side surface of each semiconductor chip and the housing body assembly; and separating the housing body assembly into a plurality of optoelectronic components, each component having at least one semiconductor chip and a portion of the housing body assembly as a housing body, and each semiconductor chip not being covered by material of the housing body on a radiation emission surface of the semiconductor component, which surface is located opposite a mounting surface. The invention also relates to a semiconductor component.
    Type: Grant
    Filed: February 22, 2021
    Date of Patent: November 22, 2022
    Assignee: OSRAM OLED GMBH
    Inventors: Markus Pindl, Thomas Schwarz, Frank Singer, Sandra Sobczyk
  • Patent number: 11502113
    Abstract: An array substrate and a display panel are disclosed. The array substrate includes a base substrate, a driver circuit, and a first chip-on-film structure. The array substrate further includes a plurality of transition modules and a plurality of array lines. A gate driver on array (GOA) circuit is separate from the driver circuit to be independently electrically connected to the transition modules and is connected to the base substrate through the array lines, so that problems of occurrence of corner regions in the array lines and heat likely to be produced in the corner regions can be avoided, and display quality of the display panel can be improved.
    Type: Grant
    Filed: April 29, 2020
    Date of Patent: November 15, 2022
    Inventors: Yanan Gao, Zhe Yu, Ilgon Kim
  • Patent number: 11502165
    Abstract: The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a substrate, a first isolation layer positioned in the substrate, a first treated flowable layer positioned between the first isolation layer and the substrate, a second isolation layer positioned in the substrate, and a second treated flowable layer positioned between the second isolation layer and the substrate. A width of the first isolation layer is greater than a width of the second isolation layer, and a depth of the first isolation layer is less than a depth of the second isolation layer.
    Type: Grant
    Filed: July 8, 2020
    Date of Patent: November 15, 2022
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventor: Liang-Pin Chou
  • Patent number: 11489061
    Abstract: A transistor comprises a base layer that includes a channel region, wherein the base layer and the channel region include group III-V semiconductor material. A gate stack is above the channel region, the gate stack comprises a gate electrode and a composite gate dielectric stack, wherein the composite gate dielectric stack comprises a first large bandgap oxide layer, a low bandgap oxide layer, and a second large bandgap oxide layer to provide a programmable voltage threshold. Source and drain regions are adjacent to the channel region.
    Type: Grant
    Filed: September 24, 2018
    Date of Patent: November 1, 2022
    Assignee: Intel Corporation
    Inventors: Han Wui Then, Marko Radosavljevic, Sansaptak Dusgupta, Paul Fischer, Walid Hafez
  • Patent number: 11488841
    Abstract: Provided is a method for manufacturing a semiconductor package, the method including providing a semiconductor chip on a substrate, providing a bonding member between the substrate and the semiconductor chip, and bonding the semiconductor chip on the substrate by irradiating of a laser on the substrate. Here, the bonding member may include a thermosetting resin, a curing agent, and a laser absorbing agent.
    Type: Grant
    Filed: February 19, 2020
    Date of Patent: November 1, 2022
    Assignee: Electronics and Telecommunications Research Institute
    Inventors: Yong Sung Eom, Kwang-Seong Choi, Ki Seok Jang, Seok-Hwan Moon, Jiho Joo
  • Patent number: 11488887
    Abstract: In one example, a method includes providing a first side of a semiconductor substrate with a plurality of transistors, etching a second side of the substrate, opposite the first side, with a pattern of trenches, the trenches having a pre-defined depth and width, and providing the etched semiconductor substrate in a package. In one example, the predefined depth and width of the trenches is such so as to increase the surface area of the second side of the substrate by at least 20 percent. In one example, the method also includes providing a layer of a thermal interface material (TIM) on the second side of the substrate, including to fill at least a portion of the trenches.
    Type: Grant
    Filed: March 5, 2020
    Date of Patent: November 1, 2022
    Assignee: XILINX, INC.
    Inventors: Gamal Refai-Ahmed, Suresh Ramalingam, Boon Y. Ang, Toshiyuki Hisamura, Suresh Parameswaran, Scott McCann, Hoa Lap Do
  • Patent number: 11489052
    Abstract: The present disclosure provides a thin film transistor, a manufacturing method of the thin film transistor and a display device, configured to improve electrical property of the thin film transistor. The thin film transistor includes: an active layer, including a source and drain contact region and a channel region; a metal barrier layer, covering the source and drain contact region; a first gate insulating layer, at least covering the channel region and exposing the metal barrier layer; a gate, on the first gate insulating layer and covering the channel region; an inner layer dielectric layer, on the gate and having a through hole exposing the metal barrier layer; and a source and drain, on the inner layer dielectric layer and in contact with the metal barrier layer through the through hole.
    Type: Grant
    Filed: December 17, 2019
    Date of Patent: November 1, 2022
    Assignees: Mianyang Boe Optoelectronics Technology Co., Ltd., Beijing BOE Technology Development Co., Ltd.
    Inventors: Wenhui Liu, Linchang Zhong