Patents Examined by Mouloucoulaye Inoussa
  • Semiconductor device and method of forming protective layer around cavity of semiconductor die
    Patent number: 11804416
    Abstract: A semiconductor device has a semiconductor die with a sensor and a cavity formed into a first surface of the semiconductor die to provide access to the sensor. A protective layer is formed on the first surface of the semiconductor die around the cavity. An encapsulant is deposited around the semiconductor die. The protective layer blocks the encapsulant from entering the cavity. With the cavity clear of encapsulant, liquid or gas has unobstructed entry into cavity during operation of the semiconductor die. The clear entry for the cavity provides reliable sensor detection and measurement. The semiconductor die is disposed over a leadframe. The semiconductor die has a sensor. The protective layer can be a film. The protective layer can have a beveled surface. A surface of the leadframe can be exposed from the encapsulant. A second surface of the semiconductor die can be exposed from the encapsulant.
    Type: Grant
    Filed: August 6, 2021
    Date of Patent: October 31, 2023
    Assignee: UTAC Headquarters Pte. Ltd.
    Inventors: Saravuth Sirinorakul, Preecha Joymak, Natawat Kasikornrungroj, Wasu Aingkaew, Kawin Saiubol, Thanawat Jaengkrajarng
  • Gate isolation feature and manufacturing method thereof
    Patent number: 11799019
    Abstract: A semiconductor structure includes a plurality of fin structures extending along a first direction, a plurality of gate structure segments positioned along a line extending in a second direction, the second direction being orthogonal to the first direction, wherein the gate structure segments are separated by dummy fin structures. The semiconductor structure further includes a conductive layer disposed over both the gate structure segments and the dummy fin structures to electrically connect at least some of the gate structure segments, and a cut feature aligned with one of the dummy fin structures and positioned to electrically isolate gate structure segments on both sides of the one of the dummy fin structures.
    Type: Grant
    Filed: November 6, 2020
    Date of Patent: October 24, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Kuan-Ting Pan, Huan-Chieh Su, Jia-Chuan You, Shi Ning Ju, Kuo-Cheng Chiang, Yi-Ruei Jhan, Li-Yang Chuang, Chih-Hao Wang
  • Dipole-engineered high-k gate dielectric and method forming same
    Patent number: 11784052
    Abstract: A method includes forming an oxide layer on a semiconductor region, and depositing a first high-k dielectric layer over the oxide layer. The first high-k dielectric layer is formed of a first high-k dielectric material. The method further includes depositing a second high-k dielectric layer over the first high-k dielectric layer, wherein the second high-k dielectric layer is formed of a second high-k dielectric material different from the first high-k dielectric material, depositing a dipole film over and contacting a layer selected from the first high-k dielectric layer and the second high-k dielectric layer, performing an annealing process to drive-in a dipole dopant in the dipole film into the layer, removing the dipole film, and forming a gate electrode over the second high-k dielectric layer.
    Type: Grant
    Filed: November 10, 2020
    Date of Patent: October 10, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Te-Yang Lai, Chun-Yen Peng, Sai-Hooi Yeong, Chi On Chui
  • Method of monitoring the pressure of an aircraft tire
    Patent number: 11772434
    Abstract: A method of monitoring the pressure of a tire of an aircraft is disclosed including taking two or more pressure readings from the tire at different times; calculating an estimated deflation rate based on the pressure readings; and calculating a time for the tire to deflate to a reference pressure level based on the estimated deflation rate. Two or more temperature readings are each associated with one of the pressure readings, and the estimated deflation rate is calculated by normalising each pressure reading based on its associated temperature reading and a common reference temperature to obtain a temperature-normalised pressure reading, and calculating the estimated deflation rate based on the temperature-normalised pressure readings. The estimated deflation rate is compared with a threshold, and a warning provided if the estimated deflation rate exceeds the threshold.
    Type: Grant
    Filed: July 12, 2022
    Date of Patent: October 3, 2023
    Assignee: AIRBUS OPERATIONS LIMITED
    Inventor: Andrew Bill
  • Reducing parasitic capacitance for gate-all-around device by forming extra inner spacers
    Patent number: 11764286
    Abstract: A semiconductor device includes a plurality of nanostructures. The nanostructures each contain a semiconductive material. A plurality of first spacers circumferentially wrap around the nanostructures. A plurality of second spacers circumferentially wrap around the first spacers. A plurality of third spacers is disposed between the second spacers vertically. A gate structure surrounds the second spacers and the third spacers.
    Type: Grant
    Filed: July 19, 2021
    Date of Patent: September 19, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Kuo-Cheng Ching, Chih-Hao Wang, Shi Ning Ju, Kuan-Lun Cheng
  • Airgap isolation structures
    Patent number: 11764258
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to airgap isolation structures and methods of manufacture. The structure includes: a bulk substrate material; a first airgap isolation structure in the bulk substrate material and having a first aspect ratio; and a second airgap isolation structure in the bulk substrate material and having a second aspect ratio different from the first aspect ratio.
    Type: Grant
    Filed: December 1, 2020
    Date of Patent: September 19, 2023
    Assignee: GLOBALFOUNDRIES U.S. INC.
    Inventors: Brett T. Cucci, Siva P. Adusumilli, Johnatan A. Kantarovsky, Claire E. Kardos, Sen Liu
  • Charge trap structure with barrier to blocking region
    Patent number: 11765903
    Abstract: Various embodiments, disclosed herein, include methods and apparatus having charge trap structures, where each charge trap structure includes a dielectric barrier between a gate and a blocking dielectric on a charge trap region of the charge trap structure. In various embodiments, material of the dielectric barrier of each of the charge trap structures may have a dielectric constant greater than that of aluminum oxide. Additional apparatus, systems, and methods are disclosed.
    Type: Grant
    Filed: May 19, 2022
    Date of Patent: September 19, 2023
    Assignee: Micron Technology, Inc.
    Inventor: Chris M. Carlson
  • E-D mode 2DEG FET with gate spacer to locally tune VT and improve breakdown
    Patent number: 11757027
    Abstract: Embodiments include a transistor and methods of forming such transistors. In an embodiment, the transistor comprises a semiconductor substrate, a barrier layer over the semiconductor substrate; a polarization layer over the barrier layer, an insulating layer over the polarization layer, a gate electrode through the insulating layer and the polarization layer, a spacer along sidewalls of the gate electrode, and a gate dielectric between the gate electrode and the barrier layer.
    Type: Grant
    Filed: December 13, 2018
    Date of Patent: September 12, 2023
    Assignee: Intel Corporation
    Inventors: Rahul Ramaswamy, Nidhi Nidhi, Walid M. Hafez, Johann C. Rode, Paul Fischer, Han Wui Then, Marko Radosavljevic, Sansaptak Dasgupta
  • Tandem vision window and media display
    Patent number: 11747698
    Abstract: Disclosed herein are systems, apparatuses, methods, and non-transitory computer readable media related to a display construct coupled to a structure (e.g., a vision window). The structure can be a supportive structure such as a fixture. The display construct is configured to facilitate media display and is at least partially transparent. The vision window may be a tintable window, e.g., a window in which its tint is electrically controllable (e.g., an electrochromic window). Various interactive capabilities with the display construct are disclosed (e.g., via a touch screen).
    Type: Grant
    Filed: November 11, 2022
    Date of Patent: September 5, 2023
    Assignee: View, Inc.
    Inventors: Nitesh Trikha, Robert Michael Martinson, Anthony Young, Vinh N. Nguyen, Matthew Burton Sheffield, Chee Yung Chan, Todd Daniel Antes, Sridhar Karthik Kailasam
  • Optoelectronic semiconductor component
    Patent number: 11749776
    Abstract: A method of producing an optoelectronic semiconductor component includes providing a carrier; arranging at least one optoelectronic semiconductor chip at a top side of the carrier, wherein the semiconductor chip includes semiconductor layers deposited on a substrate; forming a shaped body around the at least one optoelectronic semiconductor chip, wherein the shaped body surrounds all side areas of the at least one optoelectronic semiconductor chip and at least some of the layers deposited on the substrate are free of the shaped body such that these layers are not covered or completely exposed; and removing the carrier.
    Type: Grant
    Filed: December 16, 2021
    Date of Patent: September 5, 2023
    Assignee: OSRAM Opto Semiconductors GmbH
    Inventors: Karl Weidner, Ralph Wirth, Axel Kaltenbacher, Walter Wegleiter, Bernd Barchmann, Oliver Wutz, Jan Marfeld
  • Tandem vision window and media display
    Patent number: 11747696
    Abstract: Disclosed herein are systems, apparatuses, methods, and non-transitory computer readable media related to a display construct coupled to a structure (e.g., a vision window). The structure can be a supportive structure such as a fixture. The display construct is configured to facilitate media display and is at least partially transparent. The vision window may be a tintable window, e.g., a window in which its tint is electrically controllable (e.g., an electrochromic window). Various interactive capabilities with the display construct are disclosed (e.g., via a touch screen).
    Type: Grant
    Filed: April 16, 2021
    Date of Patent: September 5, 2023
    Assignee: View, Inc.
    Inventors: Nitesh Trikha, Robert Michael Martinson, Anthony Young, Vinh N. Nguyen, Matthew Burton Sheffield, Chee Yung Chan, Todd Daniel Antes, Sridhar Karthik Kailasam
  • Controllers for optically-switchable devices
    Patent number: 11740529
    Abstract: This disclosure relates generally to optically-switchable devices, and more particularly, to systems, apparatus, and methods for controlling optically-switchable devices. In some implementations, the apparatus includes an interface for communicating with window controllers, and the apparatus includes one or more processors. A processor can be configured to cause status information received from a window controller to be processed. The status information can indicate at least a tint status of one or more optically-switchable devices controlled by the window controller. In response to receiving the status information, one or more tint commands can be sent via the interface to the window controller.
    Type: Grant
    Filed: November 30, 2021
    Date of Patent: August 29, 2023
    Assignee: View, Inc.
    Inventors: Stephen Clark Brown, Dhairya Shrivastava
  • Power module of double-faced cooling
    Patent number: 11735557
    Abstract: A power module according implementations of the present disclosure includes a bonding layer for bonding two adjacent members. The bonding layer is formed by melting, applying, and solidifying a bonding material that has excellent thermal conductivity and electrical conductivity. The melted bonding material includes a plurality of anti-tilting members. The two members bonded during the process of solidifying the melted bonding material are supported by the plurality of anti-tilting members. This may allow tilting caused during the formation of the bonding layer to be suppressed.
    Type: Grant
    Filed: March 19, 2021
    Date of Patent: August 22, 2023
    Assignee: LG MAGNA E-POWERTRAIN CO., LTD.
    Inventors: Siho Choi, Seongmoo Cho, Kwangsoo Kim, Gun Lee
  • Semiconductor having a backside wafer cavity for radio frequency (RF) passive device integration and/or improved cooling and process of implementing the same
    Patent number: 11735538
    Abstract: A semiconductor device configured for a radio frequency (RF) application and further configured for passive device integration and/or improved cooling includes a substrate; an active region portion arranged on the substrate, the active region portion includes at least one radio frequency (RF) transistor amplifier; a cavity arranged within the substrate; and one or more radio frequency (RF) devices arranged in the cavity.
    Type: Grant
    Filed: February 17, 2020
    Date of Patent: August 22, 2023
    Assignee: WOLFSPEED, INC.
    Inventor: Fabian Radulescu
  • Methods and systems for manufacturing pillar structures on semiconductor devices
    Patent number: 11735549
    Abstract: A method of manufacturing a semiconductor device having a conductive substrate having a first surface, a second surface opposite the first surface, and a passivation material covering a portion of the first surface can include applying a seed layer of conductive material to the first surface of the conductive substrate and to the passivation material, the seed layer having a first face opposite the conductive substrate. The method can include forming a plurality of pillars comprising layers of first and second materials. The method can include etching the seed layer to undercut the seed layer between the conductive substrate and the first material of at least one of the pillars. In some embodiments, a cross-sectional area of the seed layer in contact with the passivation material between the first material and the conductive substrate is less than the cross-sectional area of the second material.
    Type: Grant
    Filed: July 15, 2021
    Date of Patent: August 22, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Suresh Yeruva, Owen R. Fay, Sameer S. Vadhavkar, Adriel Jebin Jacob Jebaraj, Wayne H. Huang
  • Interconnect structures including self aligned vias
    Patent number: 11735468
    Abstract: Back end of line metallization structures and methods for fabricating self-aligned vias. The structures generally include a first interconnect structure disposed above a substrate. The first interconnect structure includes a metal line formed in a first interlayer dielectric. A second interconnect structure overlies the first interconnect structure. The second interconnect structure includes a second cap layer on the first interlayer dielectric, a second interlayer dielectric thereon, and at least one self-aligned via in the second interlayer dielectric conductively coupled to at least a portion of the metal line of the first interconnect structure, wherein any misalignment of the at least one self-aligned via results in the at least one self-aligned via landing on both the metal line of the first interconnect structure and the second cap layer. The second cap layer is an insulating material.
    Type: Grant
    Filed: December 3, 2021
    Date of Patent: August 22, 2023
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Chih-Chao Yang, Terry A. Spooner, Koichi Motoyama, Shyng-Tsong Chen
  • S-contact for SOI
    Patent number: 11735589
    Abstract: Systems, methods, and apparatus for an improved protection from charge injection into layers of a device using resistive structures are described. Such resistive structures, named s-contacts, can be made using simpler fabrication methods and less fabrication steps. In a case of metal-oxide-semiconductor (MOS) field effect transistors (FETs), s-contacts can be made with direct connection, or resistive connection, to all regions of the transistors, including the source region, the drain region and the gate.
    Type: Grant
    Filed: July 6, 2022
    Date of Patent: August 22, 2023
    Assignee: pSemi Corporation
    Inventors: Befruz Tasbas, Simon Edward Willard, Alain Duvallet, Sinan Goktepeli
  • Capacitor, semiconductor device, and manufacturing method of semiconductor device
    Patent number: 11729965
    Abstract: A semiconductor device that can be miniaturized or highly integrated is provided. The semiconductor device includes a transistor and a capacitor. The transistor includes a metal oxide and a first conductor that is electrically connected to the metal oxide. The capacitor includes a first insulator which is provided over the metal oxide and which the first conductor penetrates; a second insulator provided over the first insulator and including an opening reaching the first insulator and the first conductor; a second conductor in contact with an inner wall of the opening, the first insulator, and the first conductor; a third insulator provided over the second conductor; and a fourth conductor provided over the third insulator. The first insulator has higher capability of inhibiting the passage of hydrogen than the second insulator.
    Type: Grant
    Filed: June 27, 2022
    Date of Patent: August 15, 2023
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Yuichi Sato, Ryota Hodo, Yuta Iida, Tomoaki Moriwaka
  • Active matrix substrate
    Patent number: 11721704
    Abstract: The oxide semiconductor layer is electrically connected to a source electrode or the source bus line within the source opening formed in the lower insulating layer, each wiring line connection section includes a lower conductive portion formed using the first conductive film, the lower insulating layer extending over the lower conductive portion, an oxide connection layer formed using an oxide film the same as the oxide semiconductor layer and electrically connected to the lower conductive portion within the lower opening formed in the lower insulating layer, an insulating layer covering the oxide connection layer, and an upper conductive portion electrically connected to the oxide connection layer within the upper opening formed in the insulating layer, wherein the oxide connection layer includes a region lower in a specific resistance than the channel region of the oxide semiconductor layer.
    Type: Grant
    Filed: February 7, 2022
    Date of Patent: August 8, 2023
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Hajime Imai, Tohru Daitoh, Tetsuo Kikuchi, Masamitsu Yamanaka, Yoshihito Hara, Tatsuya Kawasaki, Masahiko Suzuki, Setsuji Nishimiya
  • Method to form air gap structure with dual dielectric layer
    Patent number: 11705396
    Abstract: Embodiments of the disclosure provide a method to form an air gap structure. An opening is formed in a first dielectric layer between adjacent conductors. A first dielectric layer is formed over the opening to fill a first portion of the opening. A remainder of the opening is free of the first dielectric layer. A second dielectric layer is formed on a top surface of the first dielectric layer, with a remainder of the opening unfilled. The second dielectric layer is devoid of wiring. The remainder of the opening below the second dielectric layer defines an air gap structure. A wiring layer is formed above the air gap structure.
    Type: Grant
    Filed: July 26, 2021
    Date of Patent: July 18, 2023
    Assignee: GlobalFoundries U.S. Inc.
    Inventors: Vincent J. McGahay, Craig R. Gruszecki, Ju Jin An, Tim H. Lee, Todd J. Van Kleeck