Patents Examined by Mounir Amer
  • Patent number: 10256211
    Abstract: An apparatus is described having a build-up layer. The build-up layer has a pad side of multiple die pressed into a bottom side of the build-up layer. The multiple die have wide pads to facilitate on wafer testing of the multiple die. The wide pads are spaced a minimum distance permitted by a manufacturing process used to manufacture their respective die. The build-up layer above the wide pads is removed. The apparatus also includes metallization on a top side of the build-up layer that substantially fills regions above the wide pads. The metallization includes lands above the wide pads and multiple wires between the wide pads.
    Type: Grant
    Filed: July 28, 2014
    Date of Patent: April 9, 2019
    Assignee: Intel Corporation
    Inventors: Chuan Hu, Chia-Pin Chiu, Johanna Swan
  • Patent number: 10217679
    Abstract: The present invention relates to a method of processing a solder masked carrier with electronic components, comprising the detection of a carrier related reference and the detection of a solder mask dependent reference, which detected reference are used for processing the position of the solder mask on the carrier. The invention also relates to an electronic component as produced with such method.
    Type: Grant
    Filed: October 8, 2014
    Date of Patent: February 26, 2019
    Assignee: Besi Netherlands B.V.
    Inventors: Jurgen Hendrikus Gerhardus Huisstede, Mark Hermans
  • Patent number: 10211284
    Abstract: A silicon carbide film has first and second main surfaces. The second main surface has an element formation surface and a termination surface. The silicon carbide film has a first range that constitutes a first main surface and an intermediate surface opposite to the first main surface, and a second range that is provided on the intermediate surface and constitutes the element formation surface. The first range includes: a first breakdown voltage holding layer, and a guard ring region partially provided at the intermediate surface in the termination portion. The second range has a second breakdown voltage holding layer. The second range has one of a structure only having the second breakdown voltage holding layer in the termination portion and a structure disposed only in the element portion of the element portion and the termination portion.
    Type: Grant
    Filed: November 27, 2013
    Date of Patent: February 19, 2019
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Takeyoshi Masuda, Keiji Wada
  • Patent number: 10204855
    Abstract: Generally discussed herein are systems and methods that can include a stretchable and bendable device. According to an example a method can include (1) depositing a first elastomer material on a panel, (2) laminating trace material on the elastomer material, (3) processing the trace material to pattern the trace material into one or more traces and one or more bond pads, (4) attaching a die to the one or more bond pads, or (5) depositing a second elastomer material on and around the one or more traces, the bonds pads, and the die to encapsulate the one or more traces and the one or more bond pads in the first and second elastomer materials.
    Type: Grant
    Filed: July 11, 2014
    Date of Patent: February 12, 2019
    Assignee: Intel Corporation
    Inventors: Alejandro Levander, Tatyana Andryushchenko, David Staines, Mauro Kobrinsky, Aleksandar Aleksov, Dilan Seneviratne, Javier Soto Gonzalez, Srinivas Pietambaram, Rafiqul Islam
  • Patent number: 10205120
    Abstract: An encapsulating method, a display panel and a display apparatus, the encapsulating method including: forming a frit layer in an encapsulating area of a first substrate; forming a glass network modifier oxide layer on the surface of the frit layer; a first-sintering for the frit layer and the glass network modifier oxide layer; and aligning and attaching the first substrate and a second substrate, and forming an encapsulating structure through irradiating the encapsulating area by a laser. The encapsulating method can improve the liquidity of the surface of the frit layer and make the surface of the frit planarization after sintering at high temperature, so that the production of the holes of the surface of the frit layer can be reduced in the process of being encapsulated by a laser, and then the effect of encapsulating is improved.
    Type: Grant
    Filed: April 23, 2015
    Date of Patent: February 12, 2019
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., ORDOS YUANSHENG OPTOELECTRONICS CO., LTD.
    Inventors: Zhiliang Jiang, Fengli Ji, Renrong Gai, Minghua Xuan
  • Patent number: 10199286
    Abstract: A method for processing a semiconductor wafer uses non-contact electrical measurements indicative of at least one tip-to-side short or leakage, at least one chamfer short or leakage, and at least one corner short or leakage, where such measurements are obtained from non-contact pads associated with respective tip-to-side short, chamfer short, and corner short test areas.
    Type: Grant
    Filed: March 31, 2018
    Date of Patent: February 5, 2019
    Assignee: PDF Solutions, Inc.
    Inventors: Stephen Lam, Dennis Ciplickas, Tomasz Brozek, Jeremy Cheng, Simone Comensoli, Indranil De, Kelvin Doong, Hans Eisenmann, Timothy Fiscus, Jonathan Haigh, Christopher Hess, John Kibarian, Sherry Lee, Marci Liao, Sheng-Che Lin, Hideki Matsuhashi, Kimon Michaels, Conor O'Sullivan, Markus Rauscher, Vyacheslav Rovner, Andrzej Strojwas, Marcin Strojwas, Carl Taylor, Rakesh Vallishayee, Larg Weiland, Nobuharu Yokoyama
  • Patent number: 10199287
    Abstract: A method for processing a semiconductor wafer uses non-contact electrical measurements indicative of at least one tip-to-side short or leakage, at least one chamfer short or leakage, and at least one via open or resistance, where such measurements are obtained from non-contact pads associated with respective tip-to-side short, chamfer short, and via open test areas.
    Type: Grant
    Filed: March 31, 2018
    Date of Patent: February 5, 2019
    Assignee: PDF Solutions, Inc.
    Inventors: Stephen Lam, Dennis Ciplickas, Tomasz Brozek, Jeremy Cheng, Simone Comensoli, Indranil De, Kelvin Doong, Hans Eisenmann, Timothy Fiscus, Jonathan Haigh, Christopher Hess, John Kibarian, Sherry Lee, Marci Liao, Sheng-Che Lin, Hideki Matsuhashi, Kimon Michaels, Conor O'Sullivan, Markus Rauscher, Vyacheslav Rovner, Andrzej Strojwas, Marcin Strojwas, Carl Taylor, Rakesh Vallishayee, Larg Weiland, Nobuharu Yokoyama
  • Patent number: 10193100
    Abstract: The present invention relates to an array substrate, a fabricating method thereof, and a display device. The array substrate comprises a thin film transistor, an auxiliary electrode which is arranged in a same layer as an active layer of the thin film transistor, and a transparent cathode which is electrically connected with the auxiliary electrode, wherein the active layer is an oxide semiconductor, and the auxiliary electrode is an electric conductor which is formed by performing a modification treatment on the oxide semiconductor. According to technical solutions of the present invention, the active layer and the auxiliary electrode are arranged in a same layer, a pattern of the active layer and the auxiliary electrode can be formed by a same etching process, and a separate process for forming the auxiliary electrode is not required, thus reducing the overall process time of the array substrate and saving the fabricating cost.
    Type: Grant
    Filed: July 20, 2015
    Date of Patent: January 29, 2019
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Yonglian Qi, Feng Zhang, Dongfang Wang
  • Patent number: 10186311
    Abstract: A semiconductor device includes a memory cell, a buffer circuit, a switch, first to p-th switch circuits, and first to p-th capacitors (p is an integer of 2 or more). The first to p-th switch circuits each include first to third terminals. The memory cell is electrically connected to a first electrode of the first capacitor and an input terminal of the buffer circuit through the switch. A second electrode of an i-th capacitor is electrically connected to a first terminal of an i-th switch circuit and a first electrode of an (i+1)th capacitor (i is an integer of 1 to (p?1)). A second electrode of the p-th capacitor is electrically connected to a first terminal of the p-th switch circuit. An output terminal of the buffer circuit is electrically connected to a second terminal of each of the first to p-th switch circuits. A third terminal of each of the first to p-th switch circuits is electrically connected to a wiring supplying a low-level potential.
    Type: Grant
    Filed: May 4, 2016
    Date of Patent: January 22, 2019
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Yutaka Shionoiri
  • Patent number: 10177338
    Abstract: The present invention provides a glass powder blend comprising glass powder and additives, wherein the additives comprise copper powder, and the copper powder accounts for 2-3 mass % based on the total amount of the glass powder blend in 100 mass %. The present invention also provides a glass powder paste and a photoelectric package. Due to the addition of copper powder to the glass powder, the melting point of the glass powder blend can be decreased, thereby lowering the temperature for melting the glass powder blend by using laser, and reducing the thermal stress generated during encapsulation.
    Type: Grant
    Filed: October 30, 2014
    Date of Patent: January 8, 2019
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Rui Hong, Dan Wang, Seiji Fujino
  • Patent number: 10170516
    Abstract: An image sensing device is provided. The image sensing device includes a substrate having a pixel array with a plurality of pixels. A light guide structure is disposed over the substrate, forming a plurality of light pipes and a plurality of reflecting portions surrounding the light pipes. The light pipes are aligned with the pixels of the pixel array. The invention also provides a method for fabricating the image sensing device.
    Type: Grant
    Filed: July 23, 2014
    Date of Patent: January 1, 2019
    Assignee: VISERA TECHNOLOGIES COMPANY LIMITED
    Inventors: Han-Lin Wu, Chin-Chuan Hsieh, Chin-Ching Chang
  • Patent number: 10170569
    Abstract: Embodiments of the disclosure generally provide methods of forming thin film transistor (TFT) device structure with good interface management between a metal electrode layer and a nearby insulating material so as to provide high electrical performance devices, or for other suitable display applications. In one embodiment, a thin film transistor structure includes a metal electrode layer disposed on a barrier layer formed above a gate insulating material layer, an interface layer disposed on the metal electrode layer, wherein the interface layer is an oxygen free dielectric material layer sized to be formed predominately on the metal electrode layer, and an insulating material layer disposed on the interface layer, wherein the insulating material layer is an oxygen containing dielectric layer.
    Type: Grant
    Filed: February 22, 2016
    Date of Patent: January 1, 2019
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Tae Kyung Won, Dong-kil Yim
  • Patent number: 10170517
    Abstract: A method for forming an image sensor device on a substrate is disclosed. The method includes (a) recessing a portion of the substrate thereby forming a first shallow trench; (b) forming a spacer layer surrounding at least part of a sidewall of the first shallow trench; and (c) forming a first deep trench that extends below the first shallow trench by further recessing the substrate while using the spacer layer as a mask.
    Type: Grant
    Filed: April 17, 2017
    Date of Patent: January 1, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yueh-Chuan Lee, Ta-Hsin Chen, Chia-Chan Chen, Chih-Huang Li, Ren-Jie Lin, Jung-I Lin
  • Patent number: 10164213
    Abstract: The present disclosure provides a method for bonding an integrated circuit (IC) chip onto a flexible display body. The method includes providing a substrate having a flexible display body thereon, and aligning a first stiffening component with the flexible display body having an IC bonding region. The method further includes attaching the first stiffening component onto a front surface of the flexible display body, and separating the substrate from the first stiffening component and the flexible display body to expose a back surface of the flexible display body; and bonding an IC chip onto the IC bonding region.
    Type: Grant
    Filed: September 18, 2015
    Date of Patent: December 25, 2018
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Liqiang Chen, Tao Sun, Baoming Cai
  • Patent number: 10163732
    Abstract: A substrate processing chamber, having a processing surface, includes a guide fixed in place relative to the substrate processing chamber and a movable pyrometer connected to the guide. The movable pyrometer is movable along a radial axis that extends approximately between a center of the processing surface and an outer surface of the processing surface. The movable pyrometer is operable to monitor temperatures inside the substrate processing chamber along the radial axis.
    Type: Grant
    Filed: October 30, 2015
    Date of Patent: December 25, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Shih-Wei Hung
  • Patent number: 10158041
    Abstract: Disclosed are a photo detector capable of adjusting sensitivity and a unit pixel of an image sensor using the photo detector.
    Type: Grant
    Filed: July 9, 2014
    Date of Patent: December 18, 2018
    Inventor: Hoon Kim
  • Patent number: 10157934
    Abstract: A vertical gate all around (VGAA) nanowire device circuit routing structure is disclosed. The circuit routing structure comprises a plurality of VGAA nanowire devices including a NMOS and a PMOS device. The devices are formed on a semiconductor-on-insulator substrate. Each device comprises a bottom plate and a top plate wherein one of the bottom and top plates serves as a drain node and the other serves as a source node. Each device further comprises a gate layer. The gate layer fully surrounds a vertical channel in the device. In one example, a CMOS circuit is formed with an oxide (OD) block layer that serves as a common bottom plate for the NMOS and PMOS devices. In another example, a CMOS circuit is formed with a top plate that serves as a common top plate for the NMOS device and the PMOS devices. In another example, a SRAM circuit is formed.
    Type: Grant
    Filed: April 5, 2017
    Date of Patent: December 18, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventor: Jhon-Jhy Liaw
  • Patent number: 10147704
    Abstract: Semiconductor devices and methods of manufacture thereof are disclosed. In some embodiments, a semiconductor device includes a first integrated circuit die, a second integrated circuit die coupled to the first integrated circuit die, and a through-via coupled between a first conductive feature of the first integrated circuit die and second conductive feature of the second integrated circuit die. A conductive shield is disposed around a portion of the through-via.
    Type: Grant
    Filed: May 17, 2016
    Date of Patent: December 4, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ching-Pin Yuan, Chen-Hua Yu, Ming-Fa Chen
  • Patent number: 10141470
    Abstract: The invention relates to a photodiode type structure (comprising: a support (100) including at least one semiconductor layer, the semiconductor layer (120) including of a first semiconductor zone (10) of a first type of conductivity and a mesa (130) in contact with the semiconductor layer (120). The mesa (130) includes of a second semiconductor zone (20), known as absorption zone, said second semiconductor zone (20) being of a second type of conductivity. The second semiconductor zone has a concentration of majority carriers such that the second semiconductor zone (30) is depleted in the absence of polarization of the structure (1). The structure (1) further comprises a third semiconductor zone (30) of the second type of conductivity made of a third material transparent in the absorbed wavelength range. The third semiconductor zone (30) is interposed between the first and the second semiconductor zones (10, 20) while being at least partially arranged in the semiconductor layer (120).
    Type: Grant
    Filed: February 15, 2017
    Date of Patent: November 27, 2018
    Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Francois Boulard, Giacomo Badano, Olivier Gravrand
  • Patent number: 10128144
    Abstract: Embodiments of the disclosure generally relate to a support cylinder used in a thermal process chamber. In one embodiment, the support cylinder includes a hollow cylindrical body comprising an inner peripheral surface, an outer peripheral surface parallel to the inner peripheral surface, wherein the inner peripheral surface and the outer peripheral surface extend along a direction parallel to a longitudinal axis of the support cylinder, and a lateral portion extending radially from the outer peripheral surface to the inner peripheral surface, wherein the lateral portion comprises a first end having a first beveled portion, a first rounded portion, and a first planar portion connecting the first beveled portion and the first rounded portion, and a second end opposing the first end, the second end having a second beveled portion, a second rounded portion, and a second planar portion connecting the second beveled portion and the second rounded portion.
    Type: Grant
    Filed: May 19, 2017
    Date of Patent: November 13, 2018
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Mehran Behdjat, Aaron Muir Hunter, Joseph M. Ranish, Norman Tam, Jeffrey Tobin, Jiping Li, Martin Tran