Abstract: A test pattern for testing a trench POLY over-etched step is provided. The test pattern is a trench (14) formed on a substrate (1); the trench (14) comprises a bottom surface and two side surfaces extending from the bottom surface; the trench (14) is formed on the substrate (1) with a preset angle of non-90° formed between the longitudinal direction (L) thereof and the longitudinal direction (X) of a wafer scribing trench. The test pattern can extend the scanning length of a step scanning equipment without changing the width of the trench.

Abstract: An electrical connection structure providing better optical properties in a display includes an electrical connection unit, an interference layer, and an electrically insulating cover. The interference layer is positioned on a side of the electrical connection unit. The electrically insulating cover is positioned on the other side of the electrical connection unit and formed to cover the electrical connection unit. The electrical connection unit includes a metal layer to reflect light. The interference layer can reflect light falling on a first region close to the electrically insulating cover. A degree of reflectance of the first region of the interference layer is equal to the reflectance of the metal layer.

Abstract: A manufacturing method of an electronic device includes: providing a substrate; forming a source and a drain on the substrate; forming a semiconductor layer on the substrate; forming a first light sensitive material layer on the semiconductor layer; removing a first portion of the first light sensitive material layer by a first exposure and development process and maintaining a second portion of the first light sensitive material layer to serve as a first gate insulation layer; patterning the semiconductor layer to form a channel layer below the first gate insulation layer; forming a second light sensitive material layer on the substrate; removing a third portion of the second light sensitive material layer by a second exposure and development process to expose at least a part of the first gate insulation layer; and forming a first gate on the first gate insulation layer. An electronic device is also provided.

Abstract: The present invention provides an oxide thin film transistor and a manufacturing method thereof, an array substrate and a display device. The oxide thin film transistor of the present invention comprises a substrate, and a gate, a gate insulation layer, an oxide semiconductor active layer, a source and a drain, which are sequentially formed on the substrate, wherein, the oxide thin film transistor further comprises a transition layer formed between the oxide semiconductor active layer and the source and between the oxide semiconductor active layer and the drain, the transition layer comprises a metal layer and a protective layer, and the protective layer is in contact with the oxide semiconductor active layer, the metal layer is arranged on the protective layer and in contact with the source and the drain, and the protective layer is made of a metal oxide.

Abstract: A semiconductor memory device according to the embodiment includes a first wiring, a second wiring, a resistance change film, a metal film, and a first film. The first wiring is provided between a first interlayer insulating film and a second interlayer insulating film. The second wiring is provided intersecting with the first wiring and extends in a first direction. The resistance change film is provided between the first wiring and the second wiring. The metal film is provided between the second wiring and the resistance change film. The first film is provided between the first wirings and includes chalcogen.

Abstract: A method of manufacturing an organic light-emitting display apparatus including forming an anode on a substrate, forming a lift-off layer on the substrate including the anode, the lift-off layer including a fluoropolymer, forming a pattern on a first portion the lift-off layer overlapping the anode using a roll-to-roll stamp process, forming an organic functional layer including a light-emitting layer on the anode and on a second portion of the lift-off layer not formed with the pattern, removing the lift-off layer using a solvent including fluorine, and forming a cathode on the organic functional layer.

Abstract: A method of forming a metallization layer of an IC having a lower via level and an upper trench level is disclosed. In one aspect, the method includes applying a dual damascene process to a stack of two layers. The bottom layer includes a porous low-k dielectric in which the pores have been filled by a template material. The top layer is a template layer. This stack is obtained by depositing a template layer on top of a porous low-k dielectric and annealing in order to let the template material diffuse into the pores of the low-k layer. At the end of the anneal process, a stack of a pore-filled layer and a template layer is obtained. Vias are etched in the low-k layer and trenches are etched in the template layer. The template pore-filling protects the low-k dielectric during plasma etching, metal barrier deposition and metal deposition.

Abstract: A semiconductor device includes: a thin film transistor including an oxide semiconductor layer that is formed in an island shape and contains at least one or more elements among indium, gallium, zinc, and tin and oxygen, a source and a drain that are connected to the oxide semiconductor layer; a protective film of at least one or more layers that is formed in an upper layer of the oxide semiconductor layer, and an opening portion that is disposed in the protective film and has a position and a size for including a channel region or a back channel region of the oxide semiconductor layer; and a photodiode that is disposed in an upper layer upper than the oxide semiconductor layer of the thin film transistor and includes a hydrogenated amorphous silicon layer.

Abstract: According to one embodiment, a memory device includes first and second fin type stacked structures each includes first to i-th memory strings (i is a natural number except 1) that are stacked in a first direction, the first and second fin type stacked structures which extend in a second direction and which are adjacent in a third direction, a first portion connected to one end in the second direction of the first fin type stacked structure, a width in the third direction of the first portion being greater than a width in the third direction of the first fin type stacked structure, and a second portion connected to one end in the second direction of the second fin type stacked structure, a width in the third direction of the second portion being greater than a width in the third direction of the second fin type stacked structure.

Abstract: A method for preparing CIGS absorber layers using CIGS nanoparticles on a substrate comprises one or more annealing steps that involve heating the CIGS nanoparticle film(s) to dry the film and possibly to fuse the CIGS nanoparticles together to form CIGS crystals. Generally, at least the final annealing step will induce particle fusion to form CIGS crystals. Reactive gas annealing has been found to facilitate the growth of larger grains in the resulting CIGS absorber layers and lead to improved photovoltaic performance of those layers. It is suspected that the presence of carbon in CIGS nanoparticle films hinders grain growth and limits the size of crystals which can be obtained in CIGS films upon annealing. It has been discovered that exposing the CIGS nanoparticle films to a reactive atmosphere containing sulfur can decrease the amount of carbon in the film, resulting in the growth of larger CIGS crystals upon annealing.

Abstract: A light-emitting element includes a semiconductor layered body comprising: an n-type semiconductor layer, and p-type semiconductor layer; an insulating film disposed on the semiconductor layered body and defining at least one p-side opening above the p-type semiconductor layer and a plurality of n-side openings exposing the n-type semiconductor layer; an n-side electrode disposed on the insulating film and comprising a plurality of first n-contact portions each electrically connected to the n-type semiconductor layer through one of the plurality of n-side openings; a p-side electrode electrically connected to the p-type semiconductor layer through the at least one p-side opening; a p-side post electrode disposed on the p-side electrode; and an n-side post electrode disposed on the n-side electrode. A total area of one or more first n-contact portions located on the second side is smaller than a total area of one or more first n-contact portion located on the first side.

Abstract: Optical conversion layers based on semiconductor nanoparticles for use in lighting devices, and lighting devices including same. In various embodiments, spherical core/shell seeded nanoparticles (SNPs) or nanorod seeded nanoparticles (RSNPs) are used to form conversion layers with superior combinations of high optical density (OD), low re-absorbance and small FRET. In some embodiments, the SNPs or RSNPs form conversion layers without a host matrix. In some embodiments, the SNPs or RSNPs are embedded in a host matrix such as polymers or silicone. The conversion layers can be made extremely thin, while exhibiting the superior combinations of optical properties. Lighting devices including SNP or RSNP-based conversion layers exhibit energetically efficient superior prescribed color emission.

Abstract: Implementations of a semiconductor device package may include: a plurality of electrical contacts on a first face of a die, at least one clip electrically and mechanically coupled with at least one electrical contact on a second face of the die where the second face of the die is on an opposing side of the die from the first face of the die. The at least one clip may include at least one lead in electrical communication with the at least one electrical contact on the second face of the die. A mold compound or an encapsulating compound may be included around the die and a majority of the at least one clip where a portion of the at least one lead and a portion of the plurality of electrical contacts on the first face of the die are not overmolded or encapsulated. The semiconductor package includes no lead frame.

Abstract: A bipolar transistor and a method for fabricating a bipolar transistor are disclosed. In one embodiment the bipolar transistor includes a semiconductor body including a collector region and a base region arranged on top of the collector region, the collector region being doped with dopants of a second doping type and the base region being at least partly doped with dopants of a first doping type and an insulating spacers arranged on top of the base region. The semiconductor body further includes a semiconductor layer including an emitter region arranged on the base region and laterally enclosed by the spacers, the emitter region being doped with dopants of the second doping type forming a pn-junction with the base region, wherein the emitter region is fully located above a horizontal plane through a bottom side of the spacers.

Abstract: A method of fabricating electromagnetic radiation detection devices including: forming a first mask on a substrate; forming a structural layer on the substrate using the first mask; forming a metallic layer overlying the structural layer; removing the first mask; forming a second mask on the substrate, the second mask comprising mask openings; selectively patterning the metallic layer using the mask openings; and removing the second mask.

Abstract: A nanowire device having a plurality of internal spacers and a method for forming said internal spacers are disclosed. In an embodiment, a semiconductor device comprises a nanowire stack disposed above a substrate, the nanowire stack having a plurality of vertically-stacked nanowires, a gate structure wrapped around each of the plurality of nanowires, defining a channel region of the device, the gate structure having gate sidewalls, a pair of source/drain regions on opposite sides of the channel region; and an internal spacer on a portion of the gate sidewall between two adjacent nanowires, internal to the nanowire stack. In an embodiment, the internal spacers are formed by depositing spacer material in dimples etched adjacent to the channel region. In an embodiment, the dimples are etched through the channel region. In another embodiment, the dimples are etched through the source/drain region.

Abstract: A backside illuminated image sensor with an array of pixels formed in a substrate is provided. To improve surface planarity, bond pads formed at the periphery of the array of pixels may be recessed into a back surface of the substrate. The bond pads may be recessed into a semiconductor layer of the substrate, may be recessed into a window in the semiconductor layer, or may be recessed in a passivation layer and covered with non-conductive material such as resin. In order to further improve surface planarity, a window may be formed in the semiconductor layer at the periphery of the array of pixels, or scribe region, over alignment structures. By providing an image sensor with improved surface planarity, device yield and time-to-market may be improved, and window framing defects and microlens/color filter non-uniformity may be reduced.

Abstract: A RRAM device having a diode device structure coupled to a variable resistance layer is disclosed. The diode device structure can either be embedded into or fabricated over the substrate. A memory device having an array of said RRAM devices can be fabricated with multiple common bit lines and common word lines.

Abstract: A semiconductor device includes memory blocks each configured to comprise a pair of channels, each channel including a pipe channel formed in a pipe gate of the memory block and a drain-side channel and a source-side channel coupled to the pipe channel; first slits placed between the memory blocks adjacent to other memory blocks; and a second slit placed between the source-side channel and the drain-side channel of each pair of channels.

Abstract: Stable electrical characteristics and high reliability are provided for a semiconductor device including an oxide semiconductor. In a transistor including an oxide semiconductor layer, a buffer layer containing a constituent similar to that of the oxide semiconductor layer is provided in contact with a top surface and a bottom surface of the oxide semiconductor layer. Such a transistor and a semiconductor device including the transistor are provided. As the buffer layer in contact with the oxide semiconductor layer, a film containing an oxide of one or more elements selected from aluminum, gallium, zirconium, hafnium, and a rare earth element can be used.