Patents Examined by Mujtaba M. Chaudry
  • Patent number: 10545816
    Abstract: Hardware accelerator memory address translation fault resolution is provided. A hardware accelerator and a switchboard are in communication with a processing core. The hardware accelerator pulls an operation from a first buffer and adjusts a receive credit value in a first window context operatively coupled to the hypervisor. The receive credit value to limit a first quantity of one or more first tasks in the first buffer. The hardware accelerator determines at least one memory address translation related to the operation having a fault. The switchboard forwards the operation with the fault memory address translation from the hardware accelerator to a second buffer. The operation and the fault memory address translation are flushed from the hardware accelerator, and the operating system repairs the fault memory address translation.
    Type: Grant
    Filed: May 1, 2017
    Date of Patent: January 28, 2020
    Assignee: International Business Machines Corporation
    Inventors: Lakshminarayana B. Arimilli, Richard L. Arndt, Bartholomew Blaner
  • Patent number: 10545821
    Abstract: Examples disclosed herein relate to a fault-tolerant dot product engine. The fault-tolerant dot product engine has a crossbar array having a number l of row lines and a number n of column lines intersecting the row lines to form l×n memory locations, with each memory location having a programmable memristive element and defining a matrix value. A number l of digital-to-analog converters are coupled to the row lines of the crossbar array to receive an input signal and a number n of analog-to-digital converters are coupled to the column lines of the crossbar array to generate an output signal. The output signal is a dot product of the input signal and the matrix values in the crossbar array, wherein a number m<n of the n column lines in the crossbar array are programmed with matrix values used to detect errors in the output signal.
    Type: Grant
    Filed: July 31, 2017
    Date of Patent: January 28, 2020
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Ron M. Roth, Richard H. Henze
  • Patent number: 10536170
    Abstract: A transmitting apparatus is provided. The transmitting apparatus includes: an encoder configured to generate a low-density parity check (LDPC) codeword by LDPC encoding based on a parity check matrix; an interleaver configured to interleave the LDPC codeword; and a modulator configured to map the interleaved LDPC codeword onto a modulation symbol, wherein the modulator is further configured to map a bit included in a predetermined bit group from among a plurality of bit groups constituting the LDPC codeword onto a predetermined bit of the modulation symbol.
    Type: Grant
    Filed: June 30, 2017
    Date of Patent: January 14, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Se-ho Myung, Hong-sil Jeong, Kyung-joong Kim
  • Patent number: 10528418
    Abstract: Hardware accelerator memory address translation fault resolution is provided. A hardware accelerator and a switchboard are in communication with a processing core. The hardware accelerator determines at least one memory address translation related to an operation having a fault. The switchboard forwards the operation with the fault memory address translation from the hardware accelerator to a second buffer. The operation and the fault memory address translation are flushed from the hardware accelerator, and the operating system repairs the fault memory address translation. The switchboard forwards the operation with the repaired memory address translation from the second buffer to a first buffer and the hardware accelerator executes the operation with the repaired address.
    Type: Grant
    Filed: October 30, 2017
    Date of Patent: January 7, 2020
    Assignee: International Business Machines Corporation
    Inventors: Lakshminarayana B. Arimilli, Richard L. Arndt, Bartholomew Blaner
  • Patent number: 10528496
    Abstract: A controller may include a first encoder suitable for generating a first polar parity by performing a first polar encoding operation to respective first sections of an original message having a plurality of symbols, an interleaver suitable for generating an interleaved message by interleaving the original message according to first reliabilities, which are predetermined depending on locations of the respective symbols in the respective first sections in the original message, and second reliabilities, which are predetermined depending on locations of the respective symbols in the interleaved message, a second encoder suitable for generating a second polar parity by performing a second polar encoding operation to respective second sections included in the interleaved message and a memory interface suitable for storing the original message, the first polar parity and the second polar parity into a memory.
    Type: Grant
    Filed: May 22, 2017
    Date of Patent: January 7, 2020
    Assignees: SK hynix Inc., Korea Advanced Institute of Science and Technology
    Inventors: Jaekyun Moon, Soon-Young Kang, Sung-Whan Yoon
  • Patent number: 10530523
    Abstract: Aspects of the invention include receiving a specified number of frames of bits at a receiver. At least one of the received frames includes cyclic redundancy code (CRC) bits. The specified number of frames is based at least in part on a CRC rate. It is determined, by performing a CRC check on the received frames, whether a change in transmission errors has occurred in the received frames. An increase in the CRC rate is initiated at the receiver based at least in part on determining that a change in transmission errors has occurred in the received frames. The increase in the CRC rate is synchronized between the receiver and the transmitter; and performed in parallel with functional operations performed by the receiver.
    Type: Grant
    Filed: November 20, 2017
    Date of Patent: January 7, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Steven R. Carlough, Patrick J. Meaney, Gary Van Huben
  • Patent number: 10530396
    Abstract: Aspects of the invention include monitoring frames of bits received at a receiver for transmission errors. At least one of the received frames of bits includes cyclic redundancy code (CRC) bits for a first type of CRC check. It is determined whether a change in transmission errors has occurred in the received frames by performing the first type of CRC check based at least in part on the received CRC bits and payload bits in the received frames. A change from the first type of CRC check to a second type of CRC check is initiated at the receiver based at least in part on determining that a change in transmission errors has occurred. The change is synchronized between the receiver and the transmitter, and performed in parallel with functional operations performed by the receiver.
    Type: Grant
    Filed: November 20, 2017
    Date of Patent: January 7, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Steven R. Carlough, Patrick J. Meaney, Gary Van Huben
  • Patent number: 10503578
    Abstract: An on-chip TDDB degradation monitoring and failure early warning circuit for SoC. A control circuit module converts Q1 and Q0 signals into a switch state control signal and outputs the switch state control signal to a digital conversion module for TDDB performance degradation. A MOS transistor of a first MOS transistor circuit within the digital conversion module for TDDB performance degradation is in a stress state of a supply voltage, and a MOS transistor of a second MOS transistor circuit is in a non-stress state. The first and second MOS transistor circuits output a first frequency value and a second frequency value to the output selection module. The output selection module outputs the first frequency value from the digital conversion module to the counter B for recording, or outputs the second frequency value to the counter A for recording. The counter module determines the degradation level of TDDB performance.
    Type: Grant
    Filed: November 29, 2016
    Date of Patent: December 10, 2019
    Assignee: Fifth Electronics Research Institute of Ministry of Industry and Information Technology
    Inventors: Yiqiang Chen, Dengyun Lei, Yunfei En, Wenxiao Fang, Lichao Hao, Yun Huang, Bo Hou, Yudong Lu
  • Patent number: 10503588
    Abstract: A memory system includes a memory medium configured to store memory data and a media error correction code (ECC) decoder coupled to the memory medium. The media ECC decoder is configured to receive encoded read data from the memory medium, wherein the encoded read data is read from the stored memory data. The media ECC decoder is further configured to decode the encoded read data when the encoded read data is not poison data and a number of erroneous bits for the encoded read data is less than or equal to a threshold value. The media ECC decoder is also configured to skip decoding the encoded read data when the encoded read data is poison data and the number of erroneous bits for the encoded read data is less than or equal to the threshold value.
    Type: Grant
    Filed: April 25, 2018
    Date of Patent: December 10, 2019
    Assignee: SK hynix Inc.
    Inventor: Du Hyun Kim
  • Patent number: 10496474
    Abstract: A semiconductor storage device and a memory system having the same. The semiconductor storage device includes a memory array, an error checking/correction (ECC) element, and a setting element. The ECC element stores generated error correction codes to a storage area. The setting element can set the storage area from the external.
    Type: Grant
    Filed: May 15, 2017
    Date of Patent: December 3, 2019
    Assignee: Winbond Electronics Corp.
    Inventor: Takehiro Kaminaga
  • Patent number: 10498492
    Abstract: A method for transmitting, by a transmission entity, a packet in a system, according to an embodiment of the present invention, comprises the steps of: transmitting an automatic repeat request (ARQ) configuration (AC) message including ARQ configuration information; receiving an ARQ feedback (AF) message indicating that one or more packets are lost, the AF message including information on a propagation delay for packets to arrive at a receiving entity; identifying a delivery time of the packets between the receiving entity and the transmitting entity based on the propagation delay included in the AF message; and determining whether to transmit one or more lost packets based on the delivery time.
    Type: Grant
    Filed: July 3, 2015
    Date of Patent: December 3, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Young-Wan So, Kyung-Mo Park
  • Patent number: 10491331
    Abstract: A particular overall architecture for transmission over a bonded channel system consisting of two interconnected MoCA (Multimedia over Coax Alliance) 2.0 SoCs (Systems on a Chip) and a method and apparatus for the case of a “bonded” channel network. With a bonded channel network, the data is divided into two segments, the first of which is transported over a primary channel and the second of which is transported over a secondary channel.
    Type: Grant
    Filed: June 26, 2017
    Date of Patent: November 26, 2019
    Assignee: Entropic Communications, LLC
    Inventors: David Barr, Michail Tsatsanis, Arndt Mueller, Na Chen
  • Patent number: 10484137
    Abstract: Embodiments of the present invention provide a polar code hybrid automatic repeat request method and an apparatus. The method includes: obtaining, by a communications device, a bit sequence of retransmission information, where the bit sequence of the retransmission information includes K retransmission information bits determined from a bit sequence of first transmission information, the bit sequence of the first transmission information includes N first transmission information bits, N is a positive integer, and K is a positive integer not greater than N; performing, by the communications device, polar code encoding on the bit sequence of the retransmission information, to obtain an encoded retransmission bit sequence; and sending, by the communications device, the encoded retransmission bit sequence to another communications device.
    Type: Grant
    Filed: September 29, 2017
    Date of Patent: November 19, 2019
    Assignee: HUAWEI TECHNOLOGIES CO., LTD.
    Inventors: Bin Li, Hui Shen, Kai Chen
  • Patent number: 10476525
    Abstract: In an aspect of the disclosure, a method, a computer-readable medium, and an apparatus are provided. The apparatus may determine indices associated with m consecutive elements. In an aspect, each of the m consecutive elements may be associated with a different index. In addition, the apparatus may bit reverse a binary sequence associated with each of the m consecutive elements. In an aspect, each of the m consecutive elements may include a different binary sequence. Further, the apparatus may determine a bit-reversed order of the indices based at least in part on the bit-reversed binary sequence associated with each of the m elements. In addition, the apparatus may write each of the m consecutive elements to a different memory bank in parallel based at least in part on the bit-reversed order of the indices.
    Type: Grant
    Filed: September 14, 2017
    Date of Patent: November 12, 2019
    Assignee: QUALCOMM Incorporated
    Inventors: Gabi Sarkis, Hari Sankar, Vincent Loncke, Joseph Binamira Soriaga, Yang Yang
  • Patent number: 10454615
    Abstract: There is provided an ultra-light decoder for high speed digital communications based on block codes such as turbo product codes (TPCs). The new decoder can perform soft decision decoding without an algebraic hard decision decoder, which is the core of conventional soft decision decoders. The elimination of algebraic decoder significantly reduces the number of computations required per codeword, consequently, it reduces the decoding delay and processing power. However, reducing the decoding delay would immediately enable increasing the transmission speed, and minimize the need for large buffers at the receiver. Moreover, reducing the complexity and delay would enable using codes with high code rates to increase the system capacity, or use powerful codes with low code rates to reduce the transmission power. Such benefits can be achieved for about 1 dB loss in coding gain. There is also provided a receiver comprising the ultra-light decoder, as well as a decoding process.
    Type: Grant
    Filed: May 5, 2017
    Date of Patent: October 22, 2019
    Assignee: KHALIFA UNIVERSITY OF SCIENCE AND TECHNOLOGY
    Inventors: Arafat Jamil Al-Dweik, Husameldin Mukhtar
  • Patent number: 10439757
    Abstract: Methods and apparatus for transmitting and receiving broadcast signals are provided. The method for transmitting a broadcast signal includes encoding mobile data for forward error correction (FEC), encoding signaling data, forming data groups including the encoded mobile data and the encoded signaling data and transmitting a signal frame that includes the data groups.
    Type: Grant
    Filed: August 1, 2017
    Date of Patent: October 8, 2019
    Assignee: LG ELECTRONIC INC.
    Inventors: Jae Hyung Song, Byoung Gill Kim, Jin Woo Kim, Won Gyu Song, Hyoung Gon Lee, In Hwan Choi, Chul Kyu Mun
  • Patent number: 10432357
    Abstract: Methods, systems, and devices that support an efficient sequence-based polar code description are described. In some cases, a wireless device (e.g., a user equipment (UE) or a base station) may transmit a codeword including a set of information bits encoded using a polar code or receive a codeword including a set of information bits encoded using a polar code. As described herein, the wireless device may determine the bit locations of the information bits in the polar code based on a partition assignment vector. Specifically, the wireless device may partition bit-channels for one or more stages of polarization and assign information bits to partitions based on the partition assignment vector. Once the bit locations of the information bits are determined, the wireless device may decode a received codeword or transmit an encoded codeword based on the determined bit locations of the information bits.
    Type: Grant
    Filed: November 20, 2017
    Date of Patent: October 1, 2019
    Assignee: QUALCOMM Incorporated
    Inventors: Yang Yang, Jing Jiang, Gabi Sarkis
  • Patent number: 10432363
    Abstract: An apparatus of a memory system and an operating method thereof includes: a plurality of memory devices; and a controller including a decoder and a BER predictor, coupled with the plurality of memory devices, configured to perform a decoding iteration includes to conduct NAND read and generate NAND data; decode in accordance with the NAND data and generate decoder information by the decoder; predict a BER in accordance with at least the decode information by the BER predictor; and evaluate the predicted BER and generate evaluation result by the BER predictor.
    Type: Grant
    Filed: August 10, 2017
    Date of Patent: October 1, 2019
    Assignee: SK hynix Inc.
    Inventors: Naveen Kumar, Aman Bhatia, Yi-Min Lin
  • Patent number: 10432726
    Abstract: A computing device includes an interface configured to interface and communicate with a dispersed storage network (DSN), a memory that stores operational instructions, and processing circuitry operably coupled to the interface and to the memory. The processing circuitry is configured to execute the operational instructions to perform various operations and functions. The computing device detects a total number of errors that is associated with a set of memory devices of one or more sets of storage units (SUs) within a DSN that distributedly store a set of encoded data slices (EDSs). When the total number of errors compares unfavorably to a priority error threshold level, the computing device indicates that a minimum number of error-free EDSs are available of the set of EDSs. The computing device also selects a mechanism for data retention process from a plurality of mechanisms for data retention process and executes it.
    Type: Grant
    Filed: December 14, 2017
    Date of Patent: October 1, 2019
    Assignee: PURE STORAGE, INC.
    Inventor: Thomas D. Cocagne
  • Patent number: 10419035
    Abstract: Aspects of the invention include calculating, by a transmitter, source cyclic redundancy code (CRC) bits for payload bits. The source CRC bits include source CRC bits for a first type of CRC check and source CRC bits for a second type of CRC check. The source CRC bits are stored at the transmitter. The payload bits and the source CRC bits for the first type of CRC check are transmitted to the receiver. The receiver performs the first type of CRC check based at least in part on the payload bits and the source CRC bits for the first type of CRC check. The receiver also calculates and stores at the receiver calculated CRC bits for the second type of CRC check. If the first type of CRC check indicates an error, a comparison of the source and calculated CRC bits for the second type of CRC check is initiated.
    Type: Grant
    Filed: November 20, 2017
    Date of Patent: September 17, 2019
    Assignee: iNTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Steven R. Carlough, Patrick J. Meaney, Gary Van Huben