Patents Examined by Mujtaba M. Chaudry
  • Patent number: 10241844
    Abstract: First and second circuits in an integrated circuit that generate local hot spots are activated at different times in order to reduce heat generation within each of the first and second circuits. The first and second circuits in the integrated circuit have the same circuit architecture. The first circuit processes data during a first time period, and heat generation is reduced in the second circuit during the first time period. A data path of the data is then switched from the first circuit to the second circuit. The second circuit then processes the data during a second time period after the first time period, and heat generation is reduced in the first circuit during the second time period. The data path of the data is then switched from the second circuit back to the first circuit. The first circuit then processes the data again.
    Type: Grant
    Filed: May 11, 2017
    Date of Patent: March 26, 2019
    Assignee: Intel Corporation
    Inventors: David Mendel, Rajiv Kane
  • Patent number: 10243592
    Abstract: Embodiments of the present invention provide a method and an apparatus for generating a hybrid Polar code. The method includes: obtaining a first matrix of N×N and a sequence that includes N bits, N rows of the first matrix correspond to the N bits in the sequence in a one-to-one manner, and N is a positive integer; determining reliability of the N bits, and determining the weight of each row in the N rows of the first matrix; selecting, according to the reliability of the N bits and the weight of the N rows of the first matrix, K bits among the N bits as information bits, or selecting, according to the reliability of the N bits and the weight of the N rows of the first matrix, K rows of the first matrix to construct a second matrix of K×N used for encoding.
    Type: Grant
    Filed: March 20, 2015
    Date of Patent: March 26, 2019
    Assignee: HUAWEI TECHNOLOGIES CO., LTD.
    Inventors: Bin Li, Hui Shen
  • Patent number: 10230403
    Abstract: A soft input decoding method and a decoder for generalized concatenated (GC) codes. The GC codes are constructed from inner nested block codes, such as binary Bose-Chaudhuri-Hocquenghem, BCH, codes and outer codes, such as Reed-Solomon, RS, codes. In order to enable soft input decoding for the inner block codes, a sequential stack decoding algorithm is used. Ordinary stack decoding of binary block codes requires the complete trellis of the code. In one aspect, the present invention applies instead a representation of the block codes based on the trellizes of supercodes in order to reduce the memory requirements for the representation of the inner codes. This enables an efficient hardware implementation. In another aspect, there is provided a soft input decoding method and device employing a sequential stack decoding algorithm in combination with list-of-two decoding which is particularly well suited for applications that require very low residual error rates.
    Type: Grant
    Filed: May 15, 2017
    Date of Patent: March 12, 2019
    Inventors: Juergen Freudenberger, Jens Spinner, Christoph Baumhof
  • Patent number: 10230396
    Abstract: Methods and apparatus are disclosed for decoding low-density parity check (LDPC) encoded data using a parity check matrix having a plurality of layers. The apparatus includes a decoder having circuitry to decode, layer by layer, a LDPC codeword utilizing functional adjustments and an algorithmic approximation to belief propagation to provide an estimate of the LDPC codeword, the functional adjustments including layer specific parameters for at least two layers of the parity check matrix associated with the LDPC codeword.
    Type: Grant
    Filed: September 25, 2017
    Date of Patent: March 12, 2019
    Assignee: Microsemi Solutions (US), Inc.
    Inventors: Rino Micheloni, Alessia Marelli, Peter Z. Onufryk, Christopher I. W. Norrie
  • Patent number: 10216568
    Abstract: Hardware accelerator memory address translation fault resolution is provided. A hardware accelerator and a switchboard are in communication with a processing core. The hardware accelerator determines at least one memory address translation related to an operation having a fault. The operation and the fault memory address translation are flushed from the hardware accelerator including augmenting the operation with an entity identifier. The switchboard forwards the operation with the fault memory address translation and the entity identifier from the hardware accelerator to a second buffer. The operating system repairs the fault memory address translation. The operating system sends the operation to the processing core utilizing an effective address based on the entity identifier. The switchboard, supported by the processing core, forwards the operation with the repaired memory address translation to a first buffer and the hardware accelerator executes the operation with the repaired address.
    Type: Grant
    Filed: October 31, 2017
    Date of Patent: February 26, 2019
    Assignee: International Business Machines Corporation
    Inventors: Lakshminarayana B. Arimilli, Richard L. Arndt, Bartholomew Blaner
  • Patent number: 10198313
    Abstract: A device that provides for redundancy of error correction encoded data includes at least one processor circuit. The at least one processor circuit is configured to perform error correction encoding on data items to generate corresponding codewords, where at least one of the data items may have a different length than at least one other of the data items and each of the codewords is the same length. The at least one processor circuit is further configured to generate a redundancy data item based at least in part on the codewords. The at least one processor circuit is further configured to write the codewords and the redundancy data item to separate blocks of at least one flash memory circuit.
    Type: Grant
    Filed: March 11, 2016
    Date of Patent: February 5, 2019
    Assignee: Western Digital Technologies, Inc.
    Inventors: Richard David Barndt, Majid Nemati Anaraki
  • Patent number: 10193566
    Abstract: An object is to enable erasure correction even at the time of a degeneration operation and reduce the number of necessary parallel media through dynamic setting of degree of redundancy. A parallel data encoding/decoding system performs parallel data transmissions using a plurality of lanes from an encoder to a decoder. The encoder encodes products of elements of an encoding vector M of symbols of each lane and a state vector U indicating validity of the symbols, and transmits the state vector U along with a transmission vector Y obtained through the encoding. The decoder decodes a subset Msub constituted of valid elements of the encoding vector M using a received reception vector Y?, the received state vector U, and an erasure vector E indicating whether each element of the transmission vector has been erased in a transmission/reception section.
    Type: Grant
    Filed: September 6, 2013
    Date of Patent: January 29, 2019
    Assignee: NIPPON TELEGRAPH AND TELEPHONE CORPORATION
    Inventors: Yoshiaki Yamada, Mitsuhiro Teshima, Kei Kitamura, Kenji Hisadome
  • Patent number: 10193579
    Abstract: According to an embodiment, a storage control device includes a controller, a compression condition determiner, a compressor, and an error correction encoder. The controller receives a write request for a data item and determines whether or not the wear degree of a target region in a storage device to which the data item is to be written is less than a threshold value. The compression condition determiner determines, based on the wear degree, an optimal compression condition out of compression conditions that include lossy compression. The compressor generates, based on the compression condition, compressed data. The error correction encoder subjects the data item to error correction and generates encoded data.
    Type: Grant
    Filed: September 7, 2016
    Date of Patent: January 29, 2019
    Assignee: Toshiba Memory Corporation
    Inventors: Keiri Nakanishi, Katsuyuki Nomura, Sho Kodama, Youhei Fukazawa, Kazuki Inoue, Kojiro Suzuki, Harutaka Goto
  • Patent number: 10180877
    Abstract: The present disclosure discloses a data storage device having error detection and correction capabilities. The data storage device includes an information encoder/decoder having error checking circuitry to determine whether one or more errors present in an input datastream. When the one or more errors are present in the input datastream, the information encoder/decoder activates error correction circuitry to correct the one or more errors when present in the input datastream. Otherwise, when the one or more errors are not present in the input datastream, the information encoder/decoder deactivates the error correction circuitry. This activation and deactivation conserves power when compared to conventional data storage devices. Any error correction circuitry, if present, in these conventional data storage devices continuously remain active even when the one or more errors are not present in the input datastream.
    Type: Grant
    Filed: May 12, 2016
    Date of Patent: January 15, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chien-Yin Liu, Hsueh-Chih Yang, Kuan-Chun Chen, Yue-Der Chih, Yi-Chun Shih
  • Patent number: 10176037
    Abstract: A disclosed transmission management system is for managing a first transmission terminal and a second transmission terminal, the first transmission terminal and the second transmission terminal communicating with each other via a relay apparatus which relays image data. The transmission management system includes a reception unit configured to receive, from the first transmission terminal, band information which indicates whether a bandwidth of communication between the relay apparatus and the first transmission terminal is equal to or narrower than a predetermined value, and a transmission unit configured to transmit, to the first transmission terminal, a message which indicates that image data transmitted from the second transmission terminal is hidden because the bandwidth is narrow in response to an event in which the reception unit receives the band information which indicates that the bandwidth is equal to or narrower than the predetermined value.
    Type: Grant
    Filed: January 14, 2016
    Date of Patent: January 8, 2019
    Assignee: Ricoh Company, Ltd.
    Inventor: Yoshinaga Kato
  • Patent number: 10177785
    Abstract: An approach for generating updated error detecting code for a partial update of data is disclosed. The techniques include receiving data representing a change to a portion of a data object, the data object having a first error detecting code, and the portion of the data object having an offset from the beginning of the data object; generating a combination term by combining the data and the portion of the data object; and computing a second error detecting code based on the combination term. The techniques may further include computing a third error detecting code by combining the first error detecting code and the second error detecting code, the third error detecting code being configured to detect an error in the data object as changed by the data, and storing the data and the third error detecting code.
    Type: Grant
    Filed: August 23, 2016
    Date of Patent: January 8, 2019
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Cyril Guyot, Lluis Pamies-Juarez
  • Patent number: 10170202
    Abstract: A memory system includes a semiconductor storage device that includes a plurality of blocks, and a controller configured to designate a block of the semiconductor storage device as a partial bad block if, after performing a write operation on the block, status information read from the semiconductor storage device indicates that the write operation failed, and read data that is returned when a read operation is performed on data written pursuant to the write operation has errors that are correctable. The controller is configured to manage a partial bad block differently from a bad block.
    Type: Grant
    Filed: August 30, 2016
    Date of Patent: January 1, 2019
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Makoto Iwai, Hideaki Tsunashima, Akio Okazaki
  • Patent number: 10162005
    Abstract: A number of embodiments include an apparatus comprising a memory array including a first memory bank and a second memory bank and a serializer/de-serializer coupled to the first memory bank and the second memory bank. The serializer/de-serializer may be configured to receive a scan vector from the first memory bank, send the scan vector to a device under test, receive scan test responses from the device under test, and send the scan test responses to the second memory bank. Scan control logic may be coupled to the serializer/de-serializer and the device under test. The scan control logic may be configured to control operation of the serializer/de-serializer and send a scan chain control signal to the device under test, wherein the scan chain control signal is to initiate performance of a scan chain operation using the scan vector.
    Type: Grant
    Filed: August 9, 2017
    Date of Patent: December 25, 2018
    Assignee: Micron Technology, Inc.
    Inventor: Joshua E. Alzheimer
  • Patent number: 10152376
    Abstract: A method comprising: receiving an I/O request for object data; determining one or more data fragments wherein the object data is stored; determining that one or more of the data fragments are unavailable; determining, from within the one or more unavailable data fragments, a set of slices storing the object data, each slice comprising k small data fragments and m coded fragments; for each slice, retrieving at least k small data and coded fragments within the slice from storage; and recovering a segment of the object data using the retrieved small data and coded fragments. A related system and computer program product are also described.
    Type: Grant
    Filed: January 5, 2017
    Date of Patent: December 11, 2018
    Assignee: EMC IP HOLDING COMPANY LLC
    Inventors: Mikhail Danilov, Konstantin Buinov, Andrey Fomin, Andrey Kurilov, Maxim Trusov
  • Patent number: 10153787
    Abstract: An apparatus and a method. The apparatus includes a receiver to receive a polar codeword of length mj; a processor configured to determine a decoding node tree structure with mj leaf nodes for the received codeword, and receive i indicating a level at which parallelism of order m is applied to the decoding node tree structure, wherein i indicates levels of the decoding node tree structure, and wherein the mj leaf nodes are at level j; and m successive cancellation list decoders (SCLDs) applied to each child node of each node in the decoding node tree structure at level i?1, wherein each of the m SCLDs executes in parallel to determine log likelihood ratios (LLRs) for a codeword of length mj-i, and wherein each of the m SCLDs uses LLRs of an associated parent node without using a hard decision or a soft reliability estimate of any other node of the other m SCLDs.
    Type: Grant
    Filed: January 4, 2017
    Date of Patent: December 11, 2018
    Assignee: Samsung Electronics Co., Ltd
    Inventors: Mostafa El-Khamy, Hsien-Ping Lin, Jungwon Lee
  • Patent number: 10152249
    Abstract: The present disclosure provides a data storage system including a data memory device and controller having interface error detection and handling logic. In one example, a solid-state data memory device is provided and includes a semiconductor package. A memory array is provided in the semiconductor package and an interface is provided that is communicatively couplable to a device bus for receiving data to be stored to the memory array. An error detection component is provided in the semiconductor package and is associated with the interface of the solid-state data memory device. The error detection component is configured to detect errors occurring on data received at the interface prior to the data being stored to the memory array.
    Type: Grant
    Filed: September 21, 2016
    Date of Patent: December 11, 2018
    Assignee: Seagate Technology LLC
    Inventor: Jon David Trantham
  • Patent number: 10146482
    Abstract: In a network storage device that includes a plurality of data storage drives, error correction and/or recovery of data stored on one of the plurality of data storage drives is performed cooperatively by the drive itself and by a storage host that is configured to manage storage in the plurality of data storage drives. When an error-correcting code (ECC) operation performed by the drive cannot correct corrupted data stored on the drive, the storage host can attempt to correct the corrupted data based on parity and user data stored on the remaining data storage drives. In some embodiments, data correction can be performed iteratively between the drive and the storage host. Furthermore, the storage host can control latency associated with error correction by selecting a particular error correction process.
    Type: Grant
    Filed: July 31, 2015
    Date of Patent: December 4, 2018
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Daisuke Hashimoto, Hironori Uchikawa
  • Patent number: 10140179
    Abstract: A method and system are disclosed for providing combined error code protection and subgroup parity protection for a given group of n bits. The method comprises the steps of identifying a number, m, of redundant bits for said error protection; and constructing a matrix P, wherein multiplying said given group of n bits with P produces m redundant error correction code (ECC) protection bits, and two columns of P provide parity protection for subgroups of said given group of n bits. In the preferred embodiment of the invention, the matrix P is constructed by generating permutations of m bit wide vectors with three or more, but an odd number of, elements with value one and the other elements with value zero; and assigning said vectors to rows of the matrix P.
    Type: Grant
    Filed: December 17, 2015
    Date of Patent: November 27, 2018
    Assignee: International Business Machines Corporation
    Inventors: Alan Gara, Dong Chen, Philip Heidelberger, Martin Ohmacht
  • Patent number: 10128870
    Abstract: Systems and methods for maximizing read performance of error detection code are provided. More particularly, systems and methods for maximizing read performance of Reed Solomon Based code are provided.
    Type: Grant
    Filed: May 5, 2016
    Date of Patent: November 13, 2018
    Assignee: LOCKHEED MARTIN CORPORATION
    Inventor: Richard C. Vanhall
  • Patent number: 10114698
    Abstract: A method for use in a dispersed storage network operates to identify missing, out-of-date or otherwise compromised encoded data slices in a dispersed storage network (DSN), and when a decode threshold of encoded data slices is not available to rebuild an associated data object, determine whether a data loss event has occurred. When a data loss event is determined to have occurred the method continues by initiating a process to recover all or some of the lost data and may include notification to DSN entities that a data loss event has occurred.
    Type: Grant
    Filed: January 5, 2017
    Date of Patent: October 30, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Greg R. Dhuse, Wesley B. Leggette, Jason K. Resch