Abstract: A circuit includes a plurality of anti-fuse cells coupled to a first selection circuit, a plurality of magnetic random-access memory (MRAM) cells coupled to a second selection circuit, an amplifier including a first input terminal coupled to each of the first and second selection circuits, an analog-to-digital converter (ADC) including input terminals coupled to output terminals of the amplifier, and a comparator including a first input port coupled to an output port of the ADC. The amplifier, ADC, and comparator are configured to output data bits from the comparator responsive to current levels received from the first selection circuit at the first input terminal of the amplifier and first voltage levels received from the second selection circuit at the first input terminal of the amplifier.

Abstract: A memory device, such as an MRAM memory, includes a memory array with a plurality of bit cells. The memory array is configured to store trimming information and store user data. A sense amplifier is configured to read the trimming information from the memory array, and a trimming register is configured to receive the trimming information from the sense amplifier. The sense amplifier is configured to receive the trimming information from the trimming register so as to operate in a trimmed mode for reading the user data from the memory array.

Abstract: A pipe latch circuit may include first and second latching circuit groups. The first latching circuit group may control a latching operation and an output operation based on a plurality of pipe input control signals. The second latching circuit group may control a latching operation and an output operation based on the plurality of pipe input control signals and a plurality of pipe output control signals.

Abstract: An MRAM cell includes a switch unit configured to determine opening and closing thereof by a word line voltage and to activate a current path between a bit line and a bit line bar in an opened state thereof, first and second MTJs having opposite states, respectively, and connected in series between the bit line and the bit line bar, to constitute a storage node, and a sensing line configured to be activated in a reading mode of the MRAM cell, thereby creating data reading information based on a voltage between the first and second MTJs, wherein the first and second MTJs have different ones of a low resistance state and a high resistance state, respectively, in accordance with a voltage drop direction between the bit line and the bit line bar, thereby storing data of 0 or 1.

Abstract: A capacitive synaptic component consisting of a layered structure composed of a gate electrode, having a first dielectric layer connected to the gate electrode, a second dielectric layer and a readout electrode connected to the second dielectric layer, and an intermediate layer arranged between the first dielectric layer and the second dielectric layer. A method for writing and reading the component is also disclosed. The component addresses a high capacitive deviation ratio without changing the plate spacing, the surface area or the relative permittivity or limiting the lateral scalability by the intermediate layer having adjustable shielding behaviour in an electric field, proceeding from the gate electrode towards the readout electrode, and the intermediate layer having one or more suitable contacts that produce a charge flow into or a charge flow out of the intermediate layer.

Abstract: An in-memory computing circuit having reconfigurable logic, including: an input stage and N output stages which are cascaded. The input stage includes 2N STT-MTJs. Each output stage includes STT-MTJs, of which a quantity is equal to a half of a quantity of STT-MTJs in a just previous stage. Two STT-MTJs in the previous stage and one STT-MTJ in the subsequent stage form a double-input single-output in-memory computing unit. Each double-input single-output in-memory computing unit can implement the four logical operations, i.e., NAND, NOR, AND, and OR, under different configurations. Data storage and logical operations can be realized under the same circuit architecture, and reconfigurations among different logic can be achieved.

Abstract: A fuse programming unit, comprising: two efuse units and a mode control tube. The first efuse unit includes: one end of the first fuse forms the first end, and the second end is connected to the drain end of the first MOS. The first MOS source terminal is grounded, and the first word line formed by the gate terminal. The second efuse unit includes: the first end of the second fuse forms the second wire end, and the second end is connected to the drain end of the second MOS. The second MOS source terminal is grounded, and the gate terminal forms the second line. The source end of the mode control transistor is connected to the line end of the second efuse unit, the drain end is connected to the source end of the first MOS, and the gate end forms the correction end.

Abstract: Disclosed is threshold voltage (VT)-programmable field effect transistor (FET)-based memory cell including a first transistor and a second transistor (which has an electric-field based programmable VT) connected in series between two voltage source lines. The gates of the transistors are connected to different wordlines and a sense node is at the junction between the two transistors. In preferred embodiments, the first transistor is a PFET and the second transistor is an NFET. Different operating modes (e.g., write 0 or 1 and read) are achieved using specific combinations of voltage pulses on the wordlines and voltage source lines. The memory cell is non-volatile, exhibits relatively low leakage, and has a relatively small footprint as compared to a conventional memory cell. Also disclosed are a look-up table (LUT) incorporating multiple threshold voltage (VT)-programmable field effect transistor (FET)-based memory cells and associated methods.

Abstract: A method, device for checking data, an electronic device and a storage medium are provided. The method includes operations as follows. A memory array is read to obtain read data, and the read data is compressed to obtain first compressed data. The first compressed data is compared with second compressed data, the second compressed data being obtained by compressing written data corresponding to the read data. In responsive to that the first compressed data is consistent with the second compressed data, whether data of a predetermined bit in the read data is consistent with pre-stored original bit data is detected, to determine whether the read data is correct. It is determined that the read data is correct if the data of the predetermined bit is consistent with the pre-stored original bit data, otherwise it is determined that the read data is incorrect.

Abstract: A data storage apparatus includes an integrated circuit further including a control unit and a memory array of charge-based memory cells. The memory array includes a first subsection which is operable as a memory, and includes a second subsection which is operable as a dosimeter. The control unit is operable to provide a reference current and to conduct memory access operations to access the memory with reference to the reference current. The control unit is further operable to analyze a statistical distribution of read currents by using memory access operations in the second subsection. Said analysis involves counting of logical read errors of the memory access operations and calibrating the reference current depending on a number of counted logical read errors being indicative also of a Total Ionizing Dose, TID.

Abstract: The present disclosure generally relates to aligning non-aligned data for more efficient data reading. Data for write commands does not always perfectly align, yet the data is written in order of write command receipt. In such cases, aligned chunks of data may be split into two word lines (WLs) due to the presence of previously received smaller chunks of data. Rather than writing the data in order, the smaller chunks of data, which are non-aligned, are held in a buffer and written later to ensure that any aligned chunks of data remain aligned when written to the memory device. Once sufficient smaller chunks or data have accumulated to be aligned, or upon a need to write the smaller chunks upon reaching a threshold, the smaller chunks are written together in a single WL so as to not cause non-alignment of aligned data.

Abstract: Methods, systems, and devices for techniques for indicating row activation are described. A memory device may receive an indication associated with an activation command, which may enable the memory device to begin some aspects of an activation operation before receiving the associated activation command. The indication may include a location of a next row to access as part of the activation command. The indication may be included in a previous activation command or in a precharge command. The memory device may begin activation operations for the next row before the precharge operation of the current row is complete. The memory device may receive the activation command for the next row after receiving the indication, and may complete the activation operations upon receiving the activation command.

Abstract: Systems and method for sensing an accessed voltage value associated with a memory cell is described. In different embodiments, a memory array may include a different number of sense components. Moreover, each sense component may receive latching signals to latch the accessed voltage value of memory cells of the memory array based on different timings. For example, the memory array may latch digit line voltages of memory cells positioned farther from a respective word line driver at a later time based on a latching signal with a higher delay. Such memory arrays may include circuitry to receive and/or generate the delayed latching signals as well as selection circuitry for latching the digit line voltages based on a selected delayed latching signals.

Abstract: A data processor is for accessing a memory having a first pseudo channel and a second pseudo channel. The data processor includes at least one memory accessing agent, a memory controller, and a data fabric. The at least one memory accessing agent generates generating memory access requests including first memory access requests that access the memory. The memory controller provides memory commands to the memory in response to the first memory access requests. The data fabric routes the first memory access requests to a first downstream port in response to a corresponding first memory request accessing the first pseudo channel, and to a second downstream port in response to the corresponding first memory request accessing the second pseudo channel. The memory controller has first and second upstream ports coupled to the first and second downstream ports of the data fabric, respectively, and a downstream port coupled to the memory.

Abstract: A read operation is performed on a set of memory cells addressable by a first wordline (WL), wherein the set of memory cells is comprised by an open translation unit (TU_of memory cells of a memory device. Respective threshold voltage offset bins for each WL of a second plurality of WLs coupled to respective sets of memory cells comprised by the open TU are determined based on a threshold voltage offset bin associated with the first WL. Respective default threshold voltages for each WL of the first plurality of WLs are updated based on the respective threshold voltage offset bins for each WL of the second plurality of WLs.

Abstract: In certain aspects, a memory device includes an array of memory cells, including a first memory cell and a second memory cell, and a peripheral circuit. The peripheral circuit includes a page buffer circuit and control logic. The control logic is configured to suspend a program operation on the first memory cell responsive to receiving a suspension command indicative of executing a read operation on the second memory cell, control the page buffer circuit to release a sensing storage unit and a cache storage unit of the page buffer circuit from being occupied by a suspension of the program operation through a usage of a dynamic storage unit of the page buffer circuit during the suspension of the program operation, and initiate a read operation on the second memory cell using the sensing storage unit and the cache storage unit.

Abstract: Some memory dies in a stack can be connected externally to the stack and other memory dies in the stack can be connected internally to the stack. The memory dies that are connected externally can act as interface dies for other memory dies that are connected internally thereto. The external connections can be used for transmitting signals indicative of data to and/or from the memory dies while the memory dies in the stack can be connected by a cascading connection for transmission of other signals such as command, address, power, ground, etc.

Abstract: Systems and methods are provided for a computing-in memory circuit that includes a bit line and a plurality of computing cells connected to the bit line. Each of the plurality of computing cells includes a memory element, having a data output terminal; a logic element, having a first input terminal, a second input terminal and an output terminal, wherein the first input terminal is coupled to the data output terminal of the memory element, the second input terminal receives a select signal; and a capacitor, having a first terminal and a second terminal, where the first terminal is coupled to the output terminal of the logic element, the second terminal is coupled to the bit line. A voltage of the bit line is driven by the plurality of computing cells.

Abstract: A method for resetting an array of RAM cells by applying a sequence of N reset operations, the method including at a first reset operation, defining a first reset technique and performing the first reset operation; at a j-th reset operation of a N?1 subsequent reset operations, j being an integer between 2 and N, if a correction yield of the reset technique used at the (j?1)-th reset operation fulfils a predefined condition, applying the reset technique used at the (j?1)-th reset operation to perform the j-th reset operation, if the correction yield does not fulfil the predefined condition, defining a new reset technique and applying the new reset technique to perform the j-th reset operation, the correction yield being a cumulative correction yield or a relative correction yield, the correction yield for the N reset operations being measured prior to the first reset operation.

Abstract: A memory device includes control circuitry that executes a first programming operation and executes a second programming operation after the first programming operation. The first programming operation includes setting a threshold voltage of each of a second set of memory cells in a second section corresponding to write data, and setting a threshold voltage of each of the third set of memory cells in a third section. The second programming operation includes setting the threshold voltage of each of the second set of memory cells in a fifth section corresponding to the write data, and setting the threshold voltage of each of the third set of memory cells in a sixth section or a seventh section among a plurality of fourth sections in accordance with temperature information. The sixth section includes the same voltage range as the third section. The seventh section is higher in voltage than the third section.