Patents Examined by Muna A Techane
  • Patent number: 11100965
    Abstract: Various implementations described herein are related to a device having an array of bitcells that are accessible via wordlines and bitlines including unselected bitlines and a selected bitline. Each bitcell in the array of bitcells may be selectable via a selected wordline of the wordlines and the selected bitline of the bitlines. The device may include precharge circuitry that is configured to selectively precharge the unselected bitlines and the selected bitline before arrival of a wordline signal on the selected wordline.
    Type: Grant
    Filed: March 17, 2020
    Date of Patent: August 24, 2021
    Assignee: Arm Limited
    Inventors: Rajiv Kumar Sisodia, Disha Singh, Yattapu Viswanatha Reddy
  • Patent number: 11100981
    Abstract: A memory system includes: a memory device including a three dimensional (3D) cell array, in which memory cells having the same height are coupled to a component word line by units of rows and component word lines having the same height are coupled to a group word line; and a controller suitable for controlling the memory device to perform a program operation with a program data into memory cells coupled to a data component word line selected from a plurality of component word line included in a single group word line and to perform a dummy program operation with dummy data into memory cells coupled to remaining dummy component word lines among the plurality of component word lines.
    Type: Grant
    Filed: November 25, 2020
    Date of Patent: August 24, 2021
    Assignee: SK hynix Inc.
    Inventor: Dong-Wook Kim
  • Patent number: 11100994
    Abstract: A content addressable memory cell includes a first floating body transistor and a second floating body transistor. The first floating body transistor and the second floating body transistor are electrically connected in series through a common node. The first floating body transistor and the second floating body transistor store complementary data.
    Type: Grant
    Filed: October 22, 2020
    Date of Patent: August 24, 2021
    Assignee: Zeno Semiconductor, Inc.
    Inventors: Benjamin S. Louie, Jin-Woo Han, Yuniarto Widjaja
  • Patent number: 11094388
    Abstract: An anti-fuse device includes an anti-fuse array and a biasing circuit. The anti-fuse array includes an anti-fuse cell that has a gate node, a gate oxide layer and a source-drain node. The biasing circuit is coupled to the anti-fuse array and is configured to bias the gate node of the anti-fuse cell with a first bias voltage during a program operation, and bias the source-drain node of the anti-fuse with a second bias voltage during the program operation. A voltage level of the first bias voltage is lower than a voltage level of the second bias voltage, and a voltage difference between the first bias voltage and the second bias voltage is higher than a gate oxide breakdown voltage of the gate oxide layer.
    Type: Grant
    Filed: July 20, 2020
    Date of Patent: August 17, 2021
    Assignee: Winbond Electronics Corp.
    Inventor: Chan Jong Park
  • Patent number: 11094354
    Abstract: A quantizer generates a thermometer coded signal from an analog voltage signal. Data weighted averaging (DWA) of the thermometer coded signal is accomplished by controlling the operation of a crossbar switch controlled by a switch control signal to generate an output DWA signal. The output DWA signal is latched to generate a latched output DWA signal which is processed along with bits of the thermometer coded input signal in feedback loop to generate the switch control signal. The latching of the output DWA signal is performed in an input register of a digital-to-analog converter which operates to convert the latched output DWA signal to a feedback analog voltage from which the analog voltage signal is generated. The switch control signal specifies a bit location for a beginning logic transition of the output DWA signal cycle based on detection of an ending logic transition of the latched DWA signal.
    Type: Grant
    Filed: September 9, 2020
    Date of Patent: August 17, 2021
    Assignee: STMicroelectronics International N.V.
    Inventors: Ankur Bal, Rupesh Singh, Vivek Tripathi
  • Patent number: 11087853
    Abstract: A memory device includes a plurality of memory blocks and each memory block includes a plurality of columns of memory cells. Each column of memory cells is coupled to a corresponding bit line. Upon completion of a power-up sequence, detect if a current leakage of corresponding columns in a group of memory blocks is greater than a predetermined level. If the current leakage of the corresponding columns in the group of memory blocks is greater than the predetermined level, perform an over-erasure correction on the corresponding columns.
    Type: Grant
    Filed: September 10, 2019
    Date of Patent: August 10, 2021
    Assignee: ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC.
    Inventor: Chih-Hao Chen
  • Patent number: 11087809
    Abstract: According to one embodiment, a semiconductor memory device comprising: a first memory layer including a plurality of memory units electrically coupled to one another; a first memory area including a first memory unit for data writing of the memory units; a second memory area including a second memory unit for data reading of the memory units; and a controller configured to write data in the first memory unit, shift the data written in the first memory unit to the second memory unit, and read data written in the second memory unit.
    Type: Grant
    Filed: September 9, 2019
    Date of Patent: August 10, 2021
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Akira Katayama
  • Patent number: 11081159
    Abstract: A memory cell arrangement is provided that may include: a read-out circuit and a memory cell including: a first terminal, a second terminal, and a third terminal; the memory cell may be configured to control current flow between the second terminal and the first terminal as a function of a first voltage present at the first terminal, a third voltage applied at the third terminal, and a memory state of the memory cell. The read-out circuit is configured to: generate a characteristic voltage at the bitline by applying the third voltage at the third terminal and a second voltage at the second terminal, the characteristic voltage representing the memory state of the memory cell, and to determine the memory state of the memory cell based on sensing the characteristic voltage.
    Type: Grant
    Filed: July 15, 2020
    Date of Patent: August 3, 2021
    Assignee: FERROELECTRIC MEMORY GMBH
    Inventors: Rolf Jähne, Marko Noack
  • Patent number: 11081182
    Abstract: An integrated circuit and a computing method thereof are provided. The integrated circuit includes a memory array, word lines, bit lines and a page buffer. The memory array includes memory cells, each configured to be programmed with a weight. The word lines respectively connect a row of the memory cells. The bit lines are respectively connected with a column of the memory cells that are connected in series. More than one of the bit lines in a block of the memory array or more than one of the word lines in multiple blocks of the memory array are configured to receive input voltages. The memory cells receiving the input voltages are configured to multiply the weights stored therein and the received input voltages. The page buffer is coupled to the memory array, and configured to sense products of the weights and the input voltages.
    Type: Grant
    Filed: October 29, 2019
    Date of Patent: August 3, 2021
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventor: Hang-Ting Lue
  • Patent number: 11074954
    Abstract: According to one embodiment, a memory device includes: a first and a second interconnects; a memory cell including a variable resistive element, the memory cell between the first and second interconnects; and a write circuit including a current source circuit and a voltage source circuit, the write circuit writing data to the memory cell by using a write pulse. The write circuit supplies the write pulse to the memory cell by using the current source circuit in a first period from a first time of a start of supply of the write pulse to a second time, and supplies the write pulse to the memory cell by using the voltage source circuit in a second period from a third time to a fourth time of an end of the supply of the write pulse.
    Type: Grant
    Filed: September 10, 2019
    Date of Patent: July 27, 2021
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Yoshiaki Osada, Kosuke Hatsuda
  • Patent number: 11069398
    Abstract: A controller controlling a memory device includes an elapsed time calculator suitable for receiving an absolute time from a host whenever a state is changed between an active state and an inactive state, calculating an average hibernation elapsed time for elapsed times between first and second absolute times, and calculating a system time based on a third absolute time and the average hibernation elapsed time, and a flash translation layer suitable for controlling a program operation for the memory device in response to a program command for a memory region, calculating a program operation time for the memory region based on the system time, and controlling a read operation for the memory device using a read voltage, which is determined based on an elapsed time since the program operation time, in response to a read command for the memory region.
    Type: Grant
    Filed: December 26, 2019
    Date of Patent: July 20, 2021
    Assignee: SK hynix Inc.
    Inventor: Youn-Won Park
  • Patent number: 11069397
    Abstract: Methods, systems, and devices for phase clock correction are described. The clock correction may, in some examples, include two stages of duty cycle adjustment. In a first stage, the duty cycles of multiple clock signals may be adjusted. These clock signals may be based on an input clock signal and its complement. The duty cycle adjustment provided to a clock signal during this stage may be based on a difference between the duty cycle of the clock signal before adjustment and the duty cycle of another clock signal. In the second stage, the duty cycle of the input clock signal and its complement may be adjusted. The duty cycle adjustment provided to the input clock signal and/or its complement may be based on clock signals generated from the multiple clock signals after their duty cycles have been adjusted.
    Type: Grant
    Filed: April 1, 2019
    Date of Patent: July 20, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Martin Brox, Maksim Kuzmenka
  • Patent number: 11069384
    Abstract: Apparatuses and methods for compensation of sense amplifiers, for example, threshold voltage compensation, are disclosed. Prime memory sense amplifiers used for accessing prime memory and redundant memory sense amplifiers used for accessing redundant memory are concurrently compensated while determining whether a memory address is remapped from prime memory to redundant memory. Following the determination, sense amplifiers (e.g., prime memory sense amplifiers and/or redundant memory sense amplifiers) that are not used for accessing the memory corresponding to the memory address are precharged.
    Type: Grant
    Filed: April 1, 2019
    Date of Patent: July 20, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Shinichi Miyatake, Michael A. Shore, Adam J. Grenzebach
  • Patent number: 11056196
    Abstract: A memory device includes N rows of memory cells and N word lines coupled thereto, respectively. A method of reading data from the memory device includes: applying a first pre-pulse voltage to an nth word line while applying a second pre-pulse voltage to an adjacent word line adjacent to the nth word line, the second pre-pulse voltage exceeding the first pre-pulse voltage, and n being an integer ranging from 1 to N; grounding the nth word line while maintaining the second pre-pulse voltage on the adjacent word line; pulling a voltage on the nth word line towards a start read level; and prior to the voltage on the nth word line reaching the start read level, driving a voltage on the adjacent word line to the first pre-pulse voltage.
    Type: Grant
    Filed: January 7, 2020
    Date of Patent: July 6, 2021
    Assignee: Yangtze Memory Technologies Co., Ltd.
    Inventors: Ke Liang, Li Xiang
  • Patent number: 11049565
    Abstract: Memory devices, systems including memory devices, and methods of operating memory devices and systems are provided, in which at least a subset of a non-volatile memory array is configured to behave as a volatile memory by erasing or degrading data in the event of a changed power condition such as a power-loss event, a power-off event, or a power-on event. In one embodiment of the present technology, a memory device is provided, comprising a non-volatile memory array, and circuitry configured to store one or more addresses of the non-volatile memory array, to detect a changed power condition of the memory device, and to erase or degrade data at the one or more addresses in response to detecting the changed power condition.
    Type: Grant
    Filed: April 23, 2018
    Date of Patent: June 29, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Timothy B. Cowles, George B. Raad, James S. Rehmeyer, Jonathan S. Parry
  • Patent number: 11037609
    Abstract: A semiconductor device includes a column operation control circuit and a bank column address generation circuit. The column operation control circuit generates first and second bank address control signals as well as first and second bank control pulses from first and second bank selection signals in response to a synthesis control pulse such that data in a first bank and data in a second bank are simultaneously outputted in a first mode. The bank column address generation circuit generates first and second bank column addresses for selecting the first and second banks from a column address in response to the first and second bank address control signals.
    Type: Grant
    Filed: October 27, 2020
    Date of Patent: June 15, 2021
    Assignee: SK hynix Inc.
    Inventors: Woongrae Kim, Tae Yong Lee
  • Patent number: 11031415
    Abstract: According to one embodiment, in a semiconductor storage device, a peripheral circuit supplies a first voltage to a second region when supplying a select potential to a region corresponding to the second region, in a second conductive layer. The peripheral circuit supplies a second voltage higher than the first voltage to a first region when supplying a select potential to a region corresponding to the first region, in the second conductive layer.
    Type: Grant
    Filed: September 4, 2019
    Date of Patent: June 8, 2021
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Yoichi Minemura, Michiaki Matsuo, Reiko Shamoto
  • Patent number: 11024374
    Abstract: A semiconductor memory device of an embodiment includes: a first wiring disposed at a first level and extending in a first direction; a second and third wirings disposed at a second level and extending in the first direction; a plurality of fourth wirings disposed at a third level and extending in a third direction; a plurality of first resistive change elements disposed in intersection regions of the first and fourth wirings; a plurality of second resistive change elements disposed in intersection regions between the second wiring and the third wiring and the fourth wirings; a first driving circuit electrically connected to the first wiring, a second driving circuit electrically connected to the second wiring, and a third driving circuit electrically connected to the third wiring; and a control circuit that controls the first driving circuit, the second driving circuit, and the third driving circuit, and also the fourth wirings.
    Type: Grant
    Filed: September 4, 2019
    Date of Patent: June 1, 2021
    Assignee: Kioxia Corporation
    Inventor: Atsushi Kawasumi
  • Patent number: 11024398
    Abstract: A semiconductor device includes a first word line configured to perform a writing operation or a programing operation, a second word line configured to perform a read operation, a first switching device including a first gate electrode and a first node, a second switching device comprising a second gate electrode and a second node, an electrical fuse (e-fuse) disposed between the first node and the second node, and a diode coupled to the first node and the first word line, wherein the first gate electrode and the second gate electrode are coupled to the second word line.
    Type: Grant
    Filed: April 15, 2020
    Date of Patent: June 1, 2021
    Assignee: KEY FOUNDRY CO., LTD.
    Inventors: Jong Min Cho, Sung Bum Park, Kee Sik Ahn, Seong Jun Park
  • Patent number: 11017839
    Abstract: A training method for a memory system is provided. The memory system includes a memory controller and a memory. The memory controller is connected with the memory. The training method includes the following steps. Firstly, the memory samples n command/address signals according to a first signal edge and a second signal edge of a clock signal to acquire a first sampled content and a second sampled content. The memory selectively outputting one of the first sampled content and the second sampled content through m data signals to the memory controller in response to a control signal. Moreover, m is larger than n and smaller than 2n.
    Type: Grant
    Filed: January 5, 2018
    Date of Patent: May 25, 2021
    Assignee: MediaTek Inc.
    Inventors: Bo-Wei Hsieh, Ching-Yeh Hsuan, Shang-Pin Chen