Patents Examined by My-Trang Nu Ton
  • Patent number: 7439786
    Abstract: A power amplification circuit includes first and second clock signal generating portions operable to produce, respectively, first and second clock signals different in frequency from each other; first and second PWM signal generating portions operable to produce first and second PWM signals based on first and second input signals using the first and second clock signals, respectively; a first switching amplifier operable to perform a switching operation in response to the first PWM signal to subject the first PWM signal to power amplification to produce a first output signal and to supply the first output signal to a first circuit load; and a second switching amplifier operable to perform a switching operation in response to the second PWM signal to subject the second PWM signal to power amplification to produce a second output signal and to supply the second output signal to a second circuit load.
    Type: Grant
    Filed: November 10, 2004
    Date of Patent: October 21, 2008
    Assignee: Sony Corporation
    Inventor: Tokihiko Sawashi
  • Patent number: 7256646
    Abstract: An differential LNA has first and second input MOS transistors, with differential inputs applied to their respective control gates and differential outputs taken at their respective drains. The gate-to-drain, Cgd, feedback capacitances of the first and second input MOS transistors are neutralized by respective gate-to-source, Cgs, capacitances in the two neutralizing MOS transistors. A first neutralizing MOS transistor has its control gate coupled to the control gate of the first input MOS transistor, its source node coupled to the drain node of the second input MOS transistor, and its drain node coupled to a fixed potential. A second neutralizing MOS transistor has its control gate coupled to the control gate of the second input MOS transistor, its source node coupled to the drain node of the first input MOS transistor, and its drain node coupled to the same fixed potential.
    Type: Grant
    Filed: June 21, 2005
    Date of Patent: August 14, 2007
    Assignee: Seiko Epson Corporation
    Inventors: Salem Eid, Gregory A. Blum
  • Patent number: 7248083
    Abstract: Systems and methods for decreasing transmission timing variations include precharging a data channel at a level before data is sent over the channel. The driver sets the level in response to the reception of a precharging control signal.
    Type: Grant
    Filed: April 2, 2004
    Date of Patent: July 24, 2007
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: In-Young Chung
  • Patent number: 7248088
    Abstract: In one aspect of the invention, a method of reducing intersymbol interference on a signal line is disclosed. A state machine records previous bits that were transmitted over the line. If the bit on the line has been static for several clock cycles, the slew rate will be increased to facilitate correct reading of the bit for the next clock cycle. If the bit on the line has been dynamic for the previous bits, the slew rate will be a lower slew rate to avoid crosstalk between neighboring lines.
    Type: Grant
    Filed: August 1, 2006
    Date of Patent: July 24, 2007
    Assignee: Micron Technology, Inc.
    Inventor: Ebrahim H. Hargan
  • Patent number: 7245168
    Abstract: A clock selection circuit and method may operate to generate a clock signal for a digital processing system. In the clock selection circuit, first and second clock control signals may be generated based on a received control signal and/or the inverse of a received clock signal. A first clock signal may be selected when the first clock control signal is activated, and may be output as the selected clock signal. A second clock signal may be selected when the second clock control signal is activated, and may be output as the selected clock signal. The selection operation of the clock selection circuit may reduce the likelihood that a glitch occurs and/or may reduce the amount of power consumed when compared to a conventional clock selection circuit.
    Type: Grant
    Filed: April 1, 2005
    Date of Patent: July 17, 2007
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Young-chul Rhee
  • Patent number: 7239190
    Abstract: A clock control circuit for reducing jitter has at least one averaging circuit for generating, and outputting from an output terminal, a signal having a time difference obtained by internally dividing a time difference between first and second signals input respectively from first and second input terminals. First and second clock signals are supplied respectively to the first and second input terminals of the timing averaging circuit, and a clock in which a time difference between pulses of the first and second clock signals is averaged is generated.
    Type: Grant
    Filed: December 28, 2004
    Date of Patent: July 3, 2007
    Assignee: NEC Electronics Corporation
    Inventor: Takanori Saeki
  • Patent number: 7236032
    Abstract: Method and apparatus for an ultra-drowsy circuit for use in lower power operational modes are described.
    Type: Grant
    Filed: June 30, 2006
    Date of Patent: June 26, 2007
    Assignee: Intel Corporation
    Inventor: Mark E. Schuelein
  • Patent number: 7233171
    Abstract: A transconductance stage is provided. The transconductance stage includes a tail current source, a differential pair, and two current mirrors. The input to each of the current mirrors is connected to the drain of a separate one of the transistors in the differential pair. The two current mirrors each have two outputs so that one of the outputs can be used to determine whether the output current exceeds a threshold (e.g. nine-tenths of the tail current). If the source current exceeds the threshold, extra source current is switched in to the output so that output source current is increased. Similarly, if the sink current exceeds the threshold, extra sink current is switched in to the output so that the output sink current is increased. This way, the transconductance stage can supply large output currents in response to a large signal input but maintains low quiescent current for small input signals.
    Type: Grant
    Filed: June 29, 2005
    Date of Patent: June 19, 2007
    Assignee: National Semiconductor Corporation
    Inventors: Stuart B. Shacter, Yinming Chen
  • Patent number: 7233197
    Abstract: Leakage currents across circuit components such as transistors are avoided by placing circuits into a low-leakage standby mode. The circuits are configured such that voltage differentials across leakage-prone circuit components are avoided when in standby mode. Various means are used to configure the circuits, such as configuration ports, data input lines, scan chains, etc. In embodiments containing reconfigurable devices, low-threshold transistors are used to implement the routing network.
    Type: Grant
    Filed: December 7, 2004
    Date of Patent: June 19, 2007
    Assignee: Panasonic Europe Ltd.
    Inventors: Alan Marshall, Andrea Olgiati, Anthony I. Stansfield
  • Patent number: 7233191
    Abstract: To turn on a JFET, a two-stage turn-on current control is employed in a JFET driver circuit and a JFET driving method, by which a shortly pulsed high sourcing current is provided to turn on the JFET rapidly and efficiently, and a continuous low sourcing current is provided after the JFET turns on for reducing the power dissipation. After the JFET turns off, a negative charge pump is also employed to promise the JFET at a turn-off state. A special power sequence is further employed to ensure the JFET could be turned off during the power supply coupled to the JFET starts up.
    Type: Grant
    Filed: May 13, 2005
    Date of Patent: June 19, 2007
    Assignee: Richtek Technology Corp.
    Inventors: Hung-I Wang, Liang-Pin Tai
  • Patent number: 7233185
    Abstract: A vernier time shifting circuit is used for fine-tuning capture of a clock signal and/or a data signal to compensate for fluctuations produced by the system or other variations within non-time invariant parts of the chip. Other variations can include process, temperature, or voltage differences. The vernier sample time shifting circuit allows shifting the signal in small steps to allow for optimal sampling.
    Type: Grant
    Filed: April 29, 2004
    Date of Patent: June 19, 2007
    Assignee: Atmel Corporation
    Inventors: John L. Fagan, Mark A. Bossard, Daniel S. Cohen
  • Patent number: 7233177
    Abstract: The present invention comprises a method and structure for programming an on-chip phase-change resistor to a target resistance. Using an off-chip precision resistor as a reference, a state-machine determines a difference between the resistance of an on-chip resistor and the target resistance. Based upon this difference, the state machine directs a pulse generator to apply set or reset pulses to the on-chip resistor in order to decrease or increase, respectively, the resistance of the resistor, as necessary. In order to program the resistance of the phase-change resistor to a tight tolerance, it is successively reset and set by applying progressively decreasing numbers of reset pulses and set pulses, respectively, until the number of set pulses is equal to one and the target resistance of the on-chip resistor is reached.
    Type: Grant
    Filed: April 4, 2005
    Date of Patent: June 19, 2007
    Assignee: International Business Machines Corporation
    Inventors: Louis C. Hsu, Brian L. Ji, Chung Hon Lam
  • Patent number: 7230470
    Abstract: A power switch, and a method, for use with a power switch having a field-effect transistor (FET) including source, drain and gate terminals. The power switch includes a first field-effect transistor (FET) having a first drain coupled to the drain terminal, a first source coupled to the source terminal, and a first gate; and, a second FET having a second drain coupled to the drain terminal, a second source coupled to the source terminal, and a second gate. The second FET has a gate length (LG) that is greater than or less than an LG of the first FET and has a length of a drain (LD) that is greater than or less than an LD of the first FET. The power switch further includes a control circuit coupled to the gate terminal, the first gate, and the second gate.
    Type: Grant
    Filed: August 29, 2005
    Date of Patent: June 12, 2007
    Assignee: Volterra Semiconductor Corporation
    Inventors: Budong You, Marco A. Zuniga
  • Patent number: 7230466
    Abstract: Provided is a data strobe signal generating circuit capable of guaranteeing a preamble time (tRPRE). The data strobe signal generating circuit includes: a strobe output driver for outputting a data strobe signal to an outside of a semiconductor device so as to indicate synchronization between an external device and data input/output; and a preamble part for maintaining an output of the strobe output driver to a predetermined logic level during a predetermined delay time from an enabling timing of the preamble signal. Accordingly, it is possible to guarantee the stable operation of the semiconductor memory even when PVT (processor, operating voltage, operating temperature) changes.
    Type: Grant
    Filed: February 24, 2005
    Date of Patent: June 12, 2007
    Assignee: Hynix Semiconductor Inc.
    Inventor: Ki-Chon Park
  • Patent number: 7224203
    Abstract: In an embodiment, a switched capacitor transformer transfers a differential reference voltage at its input ports to its output ports, where a capacitor is switched so that the capacitor is coupled to the input ports during a first portion of a cycle of operation and then coupled to the output ports during a second portion of the cycle of operation, where the first and second portions of the cycle of operation are non-overlapping. Other embodiments are described and claimed.
    Type: Grant
    Filed: October 15, 2003
    Date of Patent: May 29, 2007
    Assignee: Intel Corporation
    Inventors: Peter Hazucha, Tanay Karnik
  • Patent number: 7224196
    Abstract: A multiplicity of electronic devices is provided to generate triangular wave signals variable between an upper and lower limit voltages by charging or discharging capacitors. One of the triangular wave signals serves as a master triangular wave signal for controlling the phases of the remaining (or slave) triangular wave signals. A detection signal is generated every time the master triangular wave signal reaches predetermined threshold levels. In response to the detection signal, a capacitor associated with one slave triangular signal is promptly discharged to bring the slave triangular signal to the lower limit voltage, whereby the respective slave triangular wave signals are synchronized to be offset in phase relative to the master triangular wave signal by respective predetermined phase angles.
    Type: Grant
    Filed: September 25, 2003
    Date of Patent: May 29, 2007
    Assignee: Rohm Co., Ltd.
    Inventor: Kenichi Fukumoto
  • Patent number: 7224197
    Abstract: The present invention discloses a flip-flop implemented with metal-oxide semiconductors using a single low-voltage power supply and a control method thereof, wherein an external control signal is input to a power switch in order to turn on the power switch for an active mode or to turn off the power switch for a sleep mode and inputting an external sleep control signal; the power switch is used to control a combinational circuit to enter into the active or the sleep mode, and the combinational circuit is connected to a virtual power supply; an internal clock signal is separately input to a master stage and a slave stage of the flip-flop, and whether to enter into the sleep mode or the active mode is determined by the voltage level of the internal clock signal. In the present invention, all the logic gates of the combinational circuit are formed of low-threshold CMOS's, which enables the present invention to maintain a given operation speed at a lower voltage.
    Type: Grant
    Filed: August 26, 2005
    Date of Patent: May 29, 2007
    Assignee: National Chung Cheng University
    Inventors: Jinn-Shyan Wang, Hung-Yu Li
  • Patent number: 7224191
    Abstract: Circuitry and methods allow signal detection based entirely on differential voltage pairs. An incoming differential data signal is processed by separate full-wave rectifiers to extract high and low peak voltage envelopes. The rectifiers utilize negative feedback to ensure accurate envelope detection, and can detect peaks regardless of incoming signal polarity. The extracted envelopes are compared to a differential pair of threshold voltages. If the envelope signals have a smaller voltage difference than that of the threshold signals, the final output of the detector indicates that a loss-of-signal condition has occurred. Fully differential operation makes the detector independent of common-mode voltage, and thus more robust.
    Type: Grant
    Filed: November 17, 2006
    Date of Patent: May 29, 2007
    Assignee: Altera Corporation
    Inventors: Shoujun Wang, Bill Bereza, Tad Kwasniewski, Mashkoor Baig, Haitao Mei
  • Patent number: 7221212
    Abstract: A trimming structure for trimming functional parameters of an Integrated Circuit—IC—(100) includes a first (115a) and at least one second functional blocks (115b, . . . ,115n) with which a first (Vrg,a) and at least one second IC functional parameters (Vrg,b, . . . ,Vrg,n) are respectively associated. The trimming structure includes respective trimmable circuit structures (205a,210a, . . . ,205n,210n) included in the first and at least one second functional blocks, and trimming configuration storage (110) for storing trimming configurations for the trimmable circuit structures. A change in the trimming configuration of the first functional block causes a corresponding change in the trimming configuration of the second functional block.
    Type: Grant
    Filed: April 25, 2005
    Date of Patent: May 22, 2007
    Assignee: STMicroelectronics S.r.l.
    Inventors: Luca Crippa, Miriam Sangalli, Salvatrice Scommegna, Rino Micheloni
  • Patent number: RE45704
    Abstract: An RF switch useable up to millimeter wave frequencies and higher frequencies of 30 GHz and above. Four embodiments of the invention are configured as ground switches. Two of the ground switch embodiments are configured with a planar air bridge. Both of these embodiments are configured so that the bridge length is shortened between the transmission line and ground by introducing grounded stops. The other two ground switch embodiments include an elevated metal seesaw. In these embodiments, a shortened path to ground is provided with relatively low inductance by proper sizing and positioning of the seesaw structure. Lastly, broadband power switch embodiment is configured to utilize only a small portion of the air bridge to carry the signal. The relatively short path length results in a relatively low inductance and resistance lowers the RF power loss of the switch, thereby increasing the RF power handling capability of the switch.
    Type: Grant
    Filed: January 17, 2006
    Date of Patent: September 29, 2015
    Assignee: Northrop Grumman Systems Corporation
    Inventors: Robert B. Stokes, Alvin M. Kong