Abstract: A method and apparatus for providing non 2:1 current in a Gilbert cell mixer is disclosed. The Gilbert cell mixer provides lower voltage operation, lower LO drive and better linearity. Additional current sources are provided to drive the lower, source-coupled transistor pair thereby allowing operation of the switch transistors with lower current.

Abstract: A switch mode power converter that limits the in-rush current at start-up and reduces the occurrence of output voltage overshoot over a range of switching frequencies. The converter includes at least one Soft-Start (SS)/Frequency-Select(FS) input, at least one oscillator enable input, and an oscillator having at least one control input. Soft-start programming is linked to the frequency selection of the converter. An external capacitor connected between the SS/FS input and ground is employed to program the soft-start time, and the switching frequency generated by the oscillator is selected via the state of the SS/FS input.

Abstract: Circuitry and methods allow signal detection based entirely on differential voltage pairs. An incoming differential data signal is processed by separate full-wave rectifiers to extract high and low peak voltage envelopes. The rectifiers utilize negative feedback to ensure accurate envelope detection, and can detect peaks regardless of incoming signal polarity. The extracted envelopes are compared to a differential pair of threshold voltages. If the envelope signals have a smaller voltage difference than that of the threshold signals, the final output of the detector indicates that a loss-of-signal condition has occurred. Fully differential operation makes the detector independent of common-mode voltage, and thus more robust.

Abstract: A switched capacitor sampler circuit (220) includes an input terminal (224) for receiving an input voltage, an output terminal (226), a capacitor (222) having first and second terminals, and a switching circuit (230). The switching circuit (230) is coupled to the input terminal (224), the output terminal (226), and the first and second terminals of the capacitor (222). The switching circuit (230) stores a charge on the capacitor (222) proportional to the input voltage during a sample period, and transfers the charge from the capacitor (222) to the output terminal (226) during a transfer period subsequent to the sample period. The switching circuit (230) transfers the charge in a plurality of charge portions corresponding to a like plurality of phases of the transfer period.

Abstract: A switched capacitor input circuit (200) includes an input buffer (210), a switched capacitor sampler circuit (220), and an integrator (250). The input buffer (210) has an input terminal for receiving an input voltage, and an output terminal. The switched capacitor sampler circuit (220) has an input terminal coupled to the output terminal of the input buffer (210), and an output terminal. The switched capacitor sampler circuit (220) includes a capacitor (222) and stores a charge proportional a voltage at the output terminal of the input buffer (210) in the capacitor (222) during a sample period, and transfers the charge from the capacitor (222) to the output terminal thereof during a transfer period subsequent to the sample period in a plurality of charge portions corresponding to a like plurality of phases of the transfer period. The integrator (250) has an input terminal coupled to the output terminal of the switched capacitor sampler circuit, and an output terminal for providing an output voltage signal.

Abstract: A driver circuit is disclosed comprising an amplifier, a data DAC, and a voltage control mechanism (VCM). During a power up sequence, the VCM provides gradually increasing voltage signals to the amplifier to cause a voltage at the output of the amplifier to increase gradually. During a power down sequence, the VCM provides gradually decreasing voltage signals to the amplifier to causes the voltage at the output of the amplifier to decrease gradually. By gradually increasing and decreasing the voltage at the output of the amplifier in this way, pop noise caused by a rapid change in voltage can be reduced or even eliminated.

Abstract: Variations in the actual resistance of a target poly resistor in a semiconductor integrated circuit can be compensated for by using an active circuit that provides a negative resistance in parallel with the target resistor. This produces a tuned resistance that is closer to a desired resistance than is the actual resistance of the target resistor.

Abstract: A latch circuit 2 is described including a function path latch 4, 6, which may be in the form of a standard flip-flop, together with a data retention latch 12, 14. The reset signal nreset and the scan enable signal SE are used to control these latches to perform reset, scan, save and restore functions. The save and restore functions serve to save a data value dv from the functional path latch 4, 6 into the data retention latch 12, 14 and restore this value such that the functional path latch can be powered down without a loss of data.

Abstract: A circuit and method for performing track and hold operations utilizes a circuit configuration in which a hold capacitor connected to a track signal path can be selectively isolated from an input signal applied to a control device on a common signal path by a switching mechanism, which is used to switch the circuit between track and hold modes of operation. The switching mechanism operates to connect either the track signal path or a hold signal path to the common signal path. When the track signal path is connected to the common signal path, electrical charge is allowed to be stored in the hold capacitor. When the hold signal path is connected to the common signal path, the hold capacitor is electrically isolated to hold the stored electrical charge.

Abstract: An Input Output Block (IOB) provides programmable hysteresis to support multiple IO standards including a differential amplifier having one input coupled to an input signal and its second input coupled to a complementary input signal in the case of differential signalling, or to a reference voltage for the case of single-ended signalling, a pair of series coupled digital inverters coupled to one output of said differential amplifier, one or more transistors coupled in parallel with each input transistor of the differential amplifier, each transistor of each parallel coupled set being of a different size relative to the corresponding input transistor, the control terminal of each parallel coupled transistor in each set being coupled to the output of one of said series coupled inverters such that positive feedback is provided directly or indirectly through a selection switch, and hysteresis control bits that symmetrically enable or disable each said selection switch to provide a programmable level of hysteresis

Abstract: One embodiment of the invention provides an output driver for an integrated circuit. The output driver has a driver circuit for driving an input signal onto an output line. The driver circuit is dimensioned in such a way as to supply a current intensity dependent on the input signal to be driven and/or a potential dependent on the input signal to be driven on the output line. The current value and/or the potential value lie in a current intensity range and/or potential range defined by a predetermined specification. The driver strength of the driver circuit may be set in accordance with a control signal. A measuring circuit is provided to measure the current intensity of the current flowing on the output line and/or the potential of the output line.

Abstract: A device for converting an input signal having a bipolar pulse with a positive part and a negative part of same duration, into a difference signal includes a delay member with an input for receiving the input signal and an output. The delay member delays the input signal in order to obtain a delayed signal and outputs the delayed signal to the output. The device further includes a differential amplifier with a first input for receiving the input signal, a second input for receiving the delayed signal, and an output for outputting the difference signal formed from the input signal and the delayed signal.

Abstract: Circuits are provided for high-voltage switching in single-well CMOS processes.

Abstract: The first and second chips are provided side by side. The first chip includes: a current supply section for outputting a drive current, the current supply section including a current mirror; a current distribution MISFET; a current input MISFET for transmitting an electric current to the current supply section, the current input MISFET being connected to the current distribution MISFET; and a second current distribution MISFET. The current distribution MISFET and the second current distribution MISFET constitute a current mirror. The second chip includes a second current input MISFET which is connected to the second current distribution MISFET. The ratio between the W/L ratio of the current distribution MISFET and the W/L ratio of the current input MISFET connected thereto is the same in the first and second chips.

Abstract: A system and method are used to maintain a variance in feedback factors of an amplifier between the first and second phases either below a threshold value or within a specified range. The system includes the amplifier and first through third capacitances. The amplifier is coupled between an input node and an output node that operates during first and second phases of operation. The first capacitance is coupled across the amplifier and between the input node and the output node during the first and second phases of operation. The second capacitance is coupled to the input node during the first phase of operation. The third capacitance is coupled to one of the input and output nodes during one or both of the first and second phases of operation.

Abstract: A system and method for mutually charging switched capacitors in a switched capacitor system includes operating first and second sets of output switches during separate phases; operating first and second sets of input switches during separate phases but after the output switches are operated; and connecting the switched capacitors together after the output switches are operated but before the input switches are operated to enable them to share charge with each other toward a common mode voltage after the output switches are operated but before the input switches are operated.

Abstract: To enhance the accuracy of the delay time of the delay device by reducing the change in the power supply voltage for the delay device, and a delay device that delays an incoming transmission signal, comprising: a delay element that operates on a power supply voltage Vdd and a power supply voltage Vss and delays the transmission signal, the voltage Vdd being larger than the voltage Vss; an addition circuit that outputs to an output of the delay element, a predetermined voltage that is larger than the voltage Vss and smaller than the voltage Vdd. This delay element includes a digital circuit that outputs one of output voltages of two possible values in correspondence with an input voltage. Furthermore, the addition circuit outputs a voltage substantially similar to a threshold voltage that said output of the digital circuit inverts from one of the output voltages of two possible values to another thereof.

Abstract: Systems, methodologies, media and other embodiments associated with peak detectors are described. One exemplary system embodiment includes a voltage peak detector comprising a first detector logic configured to detect a peak voltage of an input signal. The first detector logic has a circuit behavior that produces a leakage current that may alter the peak voltage. The system can also include a second detector logic configured to replicate the circuit behavior of the first detector logic including being configured to produce a replica leakage current that is equivalent to the leakage current. The second detector logic can be operably connected to the first detector logic to cause the replica leakage current to negate the leakage current.

Abstract: A phase-jumping locked loop circuit. The locked loop circuit includes a plurality of differential amplifiers and a biasing circuit switchably coupled to each of the differential amplifiers. Each of the differential amplifiers has inputs to receive a respective pair of clock signals and outputs coupled to a common pair of output signal lines. The biasing circuit comprising a first plurality of biasing transistors coupled in parallel with one another and in series with a first set of the differential amplifiers, and a second plurality of biasing transistors coupled in parallel with one another and in series with a second set of the differential amplifiers.

Abstract: A high voltage switch circuit is disclosed for reducing high voltage junction stresses. The circuit contains a cascode device structure having one or more transistors of a same type connected in a series and being operable with a normal operating voltage and a high operating voltage. The cascode device structure comprises a high operating voltage coupled to a first end of the device structure, a low voltage coupled to a second end, and one or more control voltages controllably coupled to the gates of the transistors, wherein at least one of the control voltages coupled to the gate of at least one transistor is raised to a medium voltage level that is higher than a normal operating voltage when operating under the high operating voltage for tolerating stress imposed thereon by the high operating voltage.