Abstract: A package for a semiconductor substrate capable of being fabricated with a desirable heat radiation capability. The package includes a laminate metal substrate consisting of a metal plate, an insulator provided on the metal plate, and copper foil provided on the insulator. The metal plate is patterned to form heat spreaders/ground planes and a plurality of solitary land patterns electrically insulated from each other. The copper foil forms wings and an island pattern. The wirings and island pattern are respectively electrically connected to the land patterns and heat spreaders/ground planes by via holes and heat radiation via holes. When the island pattern is provided with ground potential, the heat spreaders/ground planes are also provided with ground potential. At the same time, the heat spreaders/ground planes efficiently release heat output from the rear of an LSI (Large Scaled Integrated Circuit) to the outside of the package.

Abstract: A surface mount semiconductor package employs locking elements for locking a plastic housing to a metal pad on which a semiconductor device is mounted. The package includes terminals having elongated crushable beads on their side surfaces adjacent the portions of the terminals just outside the plastic housing. The beads are crushed inwardly by a molding tool when it closes to provide a seal which prevents the molding plastic from bleeding out and over the sides of the terminals which extend beyond the housing and which could interfere with solder connection to the terminals.

Abstract: A protective insulating film in a semiconductor device is formed in a multi-layer structure. A lower layer portion is constituted by an organic-silane-based silicon oxide film formed by a P-CVD process using organic silane and oxygen to improve step coverage. An upper layer portion is constituted by a silane-based silicon oxide film containing excess silicon in an amount greater than that in the stoichiometric composition and formed by a P-CVD process to improve moisture resistance.

Abstract: An active type photoelectric converting device includes: a transistor formed in a surface region of a semiconductor body, the transistor accumulating signal charges generated by light incident on the transistor at the surface region of the semiconductor body in the transistor, and outputting variation of an electric signal in response to variation of the accumulated signal charges; and a first gate region including a portion of the semiconductor body, a first insulating film formed on the portion of the semiconductor body, and a first gate electrode formed the first insulating film; the gate region, provided adjacent to the transistor, for transferring the accumulated signal charges from the surface region of the semiconductor body into an inside of the semiconductor body in response to a voltage applied to the first gate electrode.

Abstract: A barrier metal layer comprises a titanium film having a surface nitrided and modified by a nitrogen compound containing nitrogen atoms, and a titanium nitride film formed on a surface of the titanium film. The titanium film and titanium nitride film are interposed between a base layer, or a lower layer of a semiconductor device, and a metal film or an upper layer of the semiconductor device.

Abstract: A hybrid (composite) integrated circuit element comprises a substrate, a thin film type integrated circuit formed on a substrate through a thin film process, and a lamination type passive circuit element such as a capacitor, inductor, resitance and a combination thereof formed on the integrated circuit. During the firing of passive circuit element in a hydrogen atmosphere, the semiconductor layer which constitutes the integrated circuit is also heat annealed. Various substrates can be used as the substrate, for example, quartz, ceramic and a cheap semiconductor substrate which has not been treated with a mirror-grinding by the use of a glass layer.

Abstract: A field effect transistor is formed on a side surface of a rectangular parallelepiped depression formed in the upper surface of a single crystalline substrate. The orientation of the side surface is substantially selected in the (100) plane or an equivalent plane of the crystalline structure of the substrate. A gate electrode is formed on the side surface with a gate insulating film therebetween. Source and Drain regions are formed in the bottom of the depression and the surface of the substrate adjacent to the depression by ion implantation with the gate electrode as a mask.

Abstract: A semiconductor device having inner leads secured via insulating adhesive films to the principal surface of a semiconductor chip and electrically connected to the respective external terminals of the semiconductor chip. The semiconductor device that can be about the size of the chip is so configured that an outer lead is continuously extended from each inner lead up to the rear surface opposite to the principal surface of the semiconductor chip in order to hold the leads and an external device in conduction.

Abstract: A high density interconnected multi-chip module is provided with a stress-reducing compliant material disposed around the chips prior to molding a polymeric substrate around the chips. Chips having contact pads are placed face down on a layer of adhesive supported by a base. A compliant material is deposited around the chips, and then a mold form is positioned around the chips. Polymeric substrate molding material is added within the mold form, and then the substrate molding material is hardened. A dielectric layer having vias aligned with predetermined ones of the contact pads and having an electrical conductor extending through the vias is situated on the hardened substrate molding material and faces of the chips. A thermal plug may be affixed to the backside of a chip prior to the addition of substrate molding material.

Abstract: A dipole component with a controlled breakover sensitivity includes a main thyristor having its gate connected to its anode through a pilot thyristor, and a triggering transistor disposed in parallel with the pilot thyristor, the base of the triggering transistor being connected to the gate of the pilot thyristor.

Abstract: This invention provides a bonded structure and a method of forming the bonded structure for joining a lead array to the conducting bonding pads of an integrated circuit element. The invention uses an anisotropic conductive film with tape automated bonding to form the bonded structure. The invention also uses integrated circuit elements having composite bumps as input/output pads. The composite bumps comprise a polymer body covered by a conductive metal coating. The invention provides a low cost method of tape automated bonding which uses lower temperature and pressure in the bonding process and provides a bond which is automatically encapsulated after the bonding has been completed. The lower temperature and pressure improve the dimensional stability of the elements of the bonded structure and the automatic encapsulation provides improved reliability.

Abstract: In a semiconductor device having alignment marks formed on a semiconductor substrate, the alignment marks include a main convex or concave alignment mark formed on said semiconductor substrate; and a plurality of minute alignment marks formed on the periphery of the main alignment mark. In areas where the minute alignment marks are formed, even when a film of aluminum or its alloy is stacked on the semiconductor substrate by high temperature sputtering, grains will not grow so as to have a large diameter. Thus, the grains created on the periphery of the main alignment mark are not erroneously recognized as the main alignment mark, thereby realizing accurate alignment.

Abstract: Solder interconnection for forming connections between an integrated semiconductor device and a carrier substrate is provided. Located on the carrier substrate are electrodes and located between the electrodes and integrated semiconductor device are solder connections that have a relatively low melting point such that when the device is in operation, the solder connection will liquify thereby permitting expansion compensation between the substrate and semiconductor device.

Abstract: In a plastic molded IC package, a metal pattern and leads are formed on a first surface of an insulating layer, and a conductive pattern connected to a semiconductor chip is formed on a second surface of the insulating layer. The conductive pattern is connected to the leads via through holes in the insulating layer.

Abstract: A vertical semiconductor device incorporates a semiconductor laminar structure including a semiconductor substrate of a first conductive type having a relatively high impurity concentration, a first semiconductor layer of the first conductive type laminated on the semiconductor substrate and having a relatively low impurity concentration, and a second semiconductor layer of the first conductive type laminated on the first semiconductor layer and having an even lower impurity concentration. A trench is formed in the semiconductor laminar structure to extend through the second semiconductor layer into the first semiconductor layer. A source region of the first conductive type is formed in a surface layer of the second semiconductor layer and the trench is filled with a gate electrode. A source electrode is formed on the source region and a drain electrode is formed on a rear surface of the semiconductor substrate.

Abstract: There is disclosed a multichip module having a sealing-cooling structure which achieves a high packaging density, high sealing-connection reliability, a low manufacturing cost and a high cooling ability. A frame 15, conforming in thermal expansion coefficient to a substrate 11, is soldered at one surface thereof to that surface of the substrate 11 on which semiconductor devices 12 are mounted. The frame 15 is fastened or fixedly secured at the other surface thereof to a lid member 17 by bolts 10 or means without any heat treatment of the whole of the module.

Abstract: A balanced frequency responsive circuit comprising circuit components formed in a semiconductor chip having first and second on-chip contact terminals which connect to first and second off-chip contact terminals, respectively, and a balanced parallel resonator circuit coupled to the contact terminals. The resonator circuit comprises a capacitance portion and an inductance portion. Part of the capacitance portion is on-chip connected between the first and second on-chip contact terminals. Another part of the capacitance portion and the inductance portion are off-chip series connected between the first and second off-chip contact terminals such that the contact terminals are comprised in a single resonant loop, essentially producing no spurious resonance signals.

Abstract: A chip resistor includes a resistor body, a wire-bonding electrode, and a soldering electrode respectively disposed on a first major surface and a second major surface of the resistor. Two electrodes are electrically connected to each other only through the resistor body. The resistor body includes an insulating substrate having a resistance layer printed on both its major surfaces and one of its side surfaces. The resistor body may include a semiconductor material. A semiconductor device having the chip resistor in which a wire from an electronic component is directly bonded to the wire-bonding electrode of the chip resistor is also disclosed.

Abstract: A carrier substrate comprises a flexible insulating substrate containing aramid fiber as a reinforcer, first bonding pads formed on one side of the flexible insulating substrate, and second bonding pads formed on the other side of the flexible insulating substrate, where the first bonding pads and the second bonding pads are electrically bonded by via-holes punched in the flexible insulating substrate. The carrier substrate and a peripheral stiffener made of a material whose thermal expansion coefficient is higher than that of the carrier substrate compose a chip carrier, and an LSI chip is mounted on the recess of the chip carrier.

Abstract: Disclosed are single electron digital devices, in which the screening lengths of individual device islands are between 0.5 and 1.0 islands. This range permits island occupancy to be bias independent, permitting the devices to hold or process digital information independent of device biases. This range of screening lengths can be effected by choice of device parameters which are sufficiently modest to permit practical fabrication of these devices.