Abstract: A display apparatus includes a display panel including a plurality of horizontal lines each including a plurality of pixels, a timing controller configured to output a polarity control signal representing a polarity corresponding to each of the plurality of horizontal lines and having a value inverted by n horizontal line units, and a source driver configured to generate a timing pulse signal sequentially representing a data charging time of each of the plurality of horizontal lines and to output a data voltage, having a polarity corresponding to each of the plurality of horizontal lines, to the display panel on the basis of the timing pulse signal. When a value of the polarity control signal is inverted, the source driver generates the timing pulse signal including a data charging time corresponding to a count value obtained by counting a number of horizontal lines after a polarity is inverted.

Abstract: A display device is disclosed. The display device comprises a display panel, a backlight unit, and a processor for driving the backlight unit so as to provide light to the display panel, wherein the processor is capable of acquiring a current duty for driving the backlight unit, on the basis of pixel information of an area excluding a text area in an input image, and driving the backlight unit on the basis of the acquired current duty.

Abstract: The display control circuit includes a drive signal generation circuit that generates a gate drive signal, a scanning line drive circuit that supplies the gate drive signal to the scanning line, and a first wire through which the gate drive signal from the drive signal generation circuit is supplied to the scanning line drive circuit. The drive signal generation circuit includes a first potential supply circuit that supplies, to the first wire, a first potential equal to or lower than an off-potential of the pixel transistor, a second potential supply circuit that supplies, to the first wire, a second potential lower than the first potential, a third potential supply circuit that supplies, to the first wire, a third potential higher than the first potential, and a fourth potential supply circuit that supplies, to the first wire, a fourth potential equal to or higher than an on-potential of the pixel transistor.

Abstract: A gate driver circuit and a display device including the gate driver circuit are disclosed. The gate driver circuit includes a stage for outputting at least two gate signals. The stage comprises, a first output buffer for outputting a first gate signal in response to a voltage of a Q node and the voltage of a Qb node; a second output buffer for outputting a second gate signal in response to the voltage of the Q node and the voltage of the Qb node; and a first diode circuit disposed between the Q node and the second output buffer.

Abstract: An input stage configured to differentially amplify an input signal and an output signal, a first current mirror and a second current mirror configured to receive a differential current from the input stage, an output stage including first and second output transistors, respectively including a gate connected to the first and second current mirrors, and a slew rate compensation circuit configured to (i) mirror a comparison current generated by comparing a voltage of a first input signal with a voltage of a second input signal, and (ii) provide the mirrored comparison current to the gate of the first or second output transistor.

Abstract: A light emitting device comprising a plurality of pixels is provided. Each of the plurality of pixels includes a light emitting element, a first transistor having a drain region connected to the light emitting element, and a second transistor having a drain region connected to a gate electrode of the first transistor. The plurality of pixels include a first pixel and a second pixel, which are adjacent to each other in a first direction. A source region of the second transistor of the first pixel and a source region of the second transistor of the second pixel share one diffusion region, and a source region, a gate electrode, and the drain region of the first transistor of the first and second pixels are sequentially arranged in one of a positive direction and a negative direction in the first direction.

Abstract: According to one embodiment, a display device including a plurality of pixels each of which includes a memory is provided. The display device includes a plurality of signal lines connected to the plurality of pixels, a signal line drive circuit configured to provide a data signal to one of the memories through one of the signal lines, a readout circuit configured to read the data signal in the memory through the signal line, and an output wire configured to externally output the data signal read by the readout circuit without passing through the signal line drive circuit.

Abstract: Disclosed is a display driving apparatus configured to provide a signal to a display panel, including an output buffer unit configured to output the source signal to the display panel for the active period and output a porch signal to the display panel for the blank period, and a low dropout (LDO) unit configured to supply the porch signal to the output buffer unit, wherein the output buffer unit includes a buffer configured to output the source signal or the porch signal to the display panel, a first switch configured to switch a connection between the LDO unit and an input line of the buffer, and a second switch configured to switch a connection between the LDO unit and an output line of the buffer, and the buffer is turned on or off according to a switching state of each of the first switch and the second switch.

Abstract: A display device includes a display panel. A fingerprint sensor package at least partially overlaps the display panel. A printed circuit board (PCB) at least partially overlaps the display panel and includes a touch sensor integrated circuit (IC). The fingerprint sensor package includes a first base having a plurality of conductive patterns, an image sensor disposed on a first surface of the first base, and a first conductive layer disposed on a second surface of the first base, at least partially overlapping with the image sensor, and electrically connected to the plurality of conductive patterns of the first base via a via electrode.

Abstract: A memory liquid crystal display including a liquid crystal panel with a built-in touch panel is provided with a state control circuit configured to switch a state of a pixel electrode between a floating state and a non-floating state. A pulse signal for touch detection is supplied to a common electrode in a touch detection period. The state control circuit changes the state of the pixel electrode from the non-floating state to the floating state before the start of the touch detection period, and changes the state of the pixel electrode from the floating state to the non-floating state after the end of the touch detection period.

Abstract: This application discloses a charge sharing circuit and charge sharing method for a display panel and a display panel. The charge sharing circuit includes a controller (250) and n sets of sharing sub-circuits (240), where each set of sharing sub-circuits (240) operates in response to a corresponding one of different polarity driving modes of pixel electrodes of the display panel, each set of sharing sub-circuits (240) includes a plurality of control elements (241), in a set of sharing sub-circuits (240), each of the data lines is connected to only one control element (241), within the same period of time, the controller drives only one set of sharing sub-circuits to operate, and n?1.

Abstract: A display panel is provided. The display panel includes a plurality of scan lines and a gate driving circuit. The scan lines are disposed on the display panel along a first direction, and respectively provide a plurality of gate driving signals. The gate driving circuit is disposed on a first side of the display panel along a second direction. The second direction intersects the first direction. The gate driving circuit includes a plurality of bias generators and a plurality of signal output circuits. The signal output circuits are divided into a plurality of groups. The bias generators respectively correspond to the groups. The bias generators generate a plurality of first bias voltages. The groups generate the gate driving signals respectively according to the first bias voltages.

Abstract: A timing controller includes a detecting circuit, a control circuit, and a compensation circuit. The timing controller reads the compensation values according to the variance between refreshing frequencies and compensate the second basic value in the white balance data driving table based on the first basic value accordingly. This could efficiently improve the grey voltage difference between after and before switching the refreshing frequency. This could efficiently improve the flicker issue.

Abstract: Embodiment of the present disclosure relate to a display device, a controller, a driving circuit, and a driving method capable of easily improving the motion picture response time through a multi-scanning operation of switching devices.

Abstract: A driving method and a driving device of a display panel are provided. According to the display panel of the present application, subpixels adjacent in a row direction of the display array have different polarities, and subpixels adjacent in a column direction of the display array have different polarities. Adjacent subpixels have different voltages and are alternately arranged with a higher voltage or a lower voltage. The common electrode voltage required for operating picture of each frame is periodically changed by the driving device, with operational picture of two frames of the display panel taken as one driving cycle. With respect to different frames, different common electrode voltages are correspondingly applied to drive subpixels in the display array, reducing the occurrence rate of viewing angle color shift of display panel.

Abstract: A gate driver, a data driver, and a display apparatus including the gate driver and the data driver, may enable a resolution of each region of a display panel to be changed. The gate driver may include a gate resolution control signal output device outputting gate resolution control signals; a gate pulse generating device generating gate pulses to be output to gate lines; and a gate line selection device selecting gate lines, to which the gate pulses output from the gate pulse generating device are to be transferred, on the basis of the gate resolution control signals. The gate pulse generating device includes gate stages generating the gate pulses. The gate line selection device includes gate serial switches; and gate parallel switches. The gate serial switches respectively connect the gate stages to the gate lines, and each of the gate parallel switches connects two adjacent gate lines.

Abstract: A pixel voltage compensation method, a pixel voltage compensator device and a display device are provided. The compensation method includes: determining a capacitance between at least one data line adjacent to a target pixel electrode and the target pixel electrode; detecting a voltage difference between a driving voltage of the data line and a driving voltage of the target pixel electrode in a period from a start of present charging of the target pixel electrode to a start of next charging; calculating a variation of the driving voltage of the target pixel electrode caused by the capacitance and the voltage difference; and compensating for the driving voltage of the target pixel electrode according to the variation. This compensation method can suppress the phenomenon of voltage cross-talk, and thus can improve the display effect of the display device.

Abstract: Self capacitance touch circuits to cancel the effects of parasitic capacitance in a touch sensitive device are disclosed. One circuit can generate a parasitic capacitance cancelation signal that can be injected into touch sensing circuitry to cancel the parasitic capacitance. Another circuit can adjust the phase and magnitude of the parasitic capacitance cancelation signal based on characteristics of channels in the touch sensing circuitry so as to fine tune the parasitic capacitance cancelations. Another circuit can drive a guard plate and touch panel electrodes so as to cancel the parasitic capacitances between the panel and the plate and between the electrodes.

Abstract: A display device comprises a power supply chip configured to output a gate-on voltage; a gamma chip configured to provide a gamma voltage; a detection resistor having a first terminal and a second terminal, wherein the first terminal is grounded; a display panel comprising a plurality of sub-pixels, a plurality of driving transistors and at least one detection transistor; wherein a gate electrode of the driving transistor receives the gate-on voltage, a first electrode of the driving transistor receives the gamma voltage, and a second electrode of the driving transistor is electrically connected to a corresponding sub-pixel; a gate electrode of the detection transistor receives the gate-on voltage, a first electrode of the detection transistor receives a test voltage, and a second electrode of the detection transistor is electrically connected to the second terminal; and a control circuit electrically connected to the second terminal.

Abstract: A shift register circuit and a method for driving the same, a gate driving circuit and a display device are provided. The shift register circuit includes an input terminal, a first control signal terminal, a second control signal terminal, and an output terminal, and further includes: an input module configured to receive an input signal input by the input terminal under the control of a first control signal input by the first control signal terminal and a second control signal input by the second control signal terminal; a storage module configured to store the input signal; a transmission module configured to transmit the input signal stored by the storage module to a preset node; and an output module configured to output a high level signal or a low level signal through the output terminal under the control of the input signal at the preset node.