Patents Examined by Nema Berezny
  • Patent number: 6734569
    Abstract: An organic chip carrier having metallic circuitry and wire bond pads thereon is bonded to an integrated circuit die by a photocurable adhesive and is electrically connected therewith by wire bonding to the wire bond pads.
    Type: Grant
    Filed: December 12, 2002
    Date of Patent: May 11, 2004
    Assignee: International Business Machines Corporation
    Inventors: Bernd Karl Appelt, Gary Alan Johansson, Konstantinos I. Papathomas
  • Patent number: 6727580
    Abstract: Spring contact elements are fabricated by depositing at least one layer of metallic material into openings defined in masking layers deposited on a surface of a substrate which may be an electronic component such as an active semiconductor device. Each spring contact element has a base end, a contact end, and a central body portion. The contact end is offset in the z-axis (at a different height) and in at least one of the x and y directions from the base end. In this manner, a plurality of spring contact elements are fabricated in a prescribed spatial relationship with one another on the substrate. The spring contact elements make temporary (i.e., pressure) or permanent (e.g., joined by soldering or brazing or with a conductive adhesive) connections with terminals of another electronic component to effect electrical connections therebetween.
    Type: Grant
    Filed: October 20, 2000
    Date of Patent: April 27, 2004
    Assignee: FormFactor, Inc.
    Inventors: Benjamin N. Eldridge, Igor Y. Khandros, Gaetan L. Mathieu, David V. Pedersen
  • Patent number: 6723629
    Abstract: The invention discloses a method for attaching solder members (114) to a substrate (112). The method includes forming a decal (110) with a plurality of solder members (114). The method further comprises aligning the decal (110) with the substrate (112) and transferring the solder members (114) on the decal (110) to the substrate (112).
    Type: Grant
    Filed: July 10, 2002
    Date of Patent: April 20, 2004
    Assignee: Texas Instruments Incorporated
    Inventors: Gregory B. Hotchkiss, Gary D. Stevens
  • Patent number: 6720257
    Abstract: A method for manufacturing a bump on a terminal face (Z1) of a semiconductor substrate (20), in which the terminal face is nucleated to generate a basic metallization through electrolytic coating of the terminal face with zincate, in such a way that zinc particles (24) electrolytically deposited on the terminal face serve as nuclei for an ensuing contact metallization (28) autocatalytically deposited on the basic metallization. In addition to the electrolytic coating with zincate, an electrolytic coating of the terminal face with palladium takes place, in such a way that, in addition to zinc particles (24), palladium particles (25) deposited on the terminal face serve as nuclei for the contact metallization subsequently autocatalytically deposited on the terminal face.
    Type: Grant
    Filed: September 28, 2001
    Date of Patent: April 13, 2004
    Assignee: Pac Tech-Packaging Technologies GmbH
    Inventor: Elke Zakel
  • Patent number: 6720197
    Abstract: The present invention provides a surface-emitting laser wherein the transverse modes are controlled and phase-synchronized laser beams are emitted from a plurality of light-emitting portions to produce what appears to be a single laser beam, and a method of fabrication thereof. This laser comprises a columnar portion (20) forming part of a reflective mirror on a light-emitting side, an embedding layer (22) surrounding the periphery of the columnar portion (20), an upper electrode (23) formed on the columnar portion (20) and the embedding layer (22), and an insulating layer (18) formed below the columnar portion (20) and the embedding layer (22). A plurality of aperture portions (23a) are formed in the upper electrode (23) above the columnar portion (20), and aperture portions (18a) are formed in the insulation layer (18) at positions corresponding to the aperture portions (23a).
    Type: Grant
    Filed: June 5, 2001
    Date of Patent: April 13, 2004
    Assignee: Seiko Epson Corporation
    Inventor: Takeo Kaneko
  • Patent number: 6709890
    Abstract: In a method of manufacturing a high frequency module to be assembled by providing, on a wiring board, a chip part and a semiconductor pellet to be bare chip mounted and then mounting the chip part and the semiconductor pellet through soldering, the wiring board is separated from a heat block with the semiconductor pellet pressurized against the wiring board in a main heating portion heating and melting a reflow solder, thereby cooling a soldering portion. Consequently, the generation of a void in the soldering portion can be prevented and the connecting reliability of the soldering portion can be enhanced. In addition, a degree of mounting horizontality of the semiconductor pellet on the wiring board can be enhanced.
    Type: Grant
    Filed: February 15, 2001
    Date of Patent: March 23, 2004
    Assignees: Renesas Technology Corporation, Hitachi Tobu Semiconductor Ltd.
    Inventors: Tsutomu Ida, Akio Ishizu, Masakazu Hashizume, Isao Hagiwara, Yoshinori Shiokawa
  • Patent number: 6706565
    Abstract: The present invention includes integrated circuit devices, synchronous-link dynamic random access memory devices, methods of forming an integrated circuit device and methods of forming a synchronous-link dynamic random access memory edge-mounted device. According to one aspect of the present invention, an integrated circuit device includes a semiconductor die and a first housing encapsulating the semiconductor die. A heat sink is positioned proximate the first housing and a second housing is formed to encapsulate at least a portion of the heat sink. The heat sink is preferably thermally coupled with the semiconductor die and configured to expel heat therefrom. Another aspect provides a method of forming an integrated circuit device including the steps of providing a semiconductor die; forming a first housing about the semiconductor die; thermally coupling a heat sink with the first housing; and forming a second housing about at least a portion of the heat sink following the thermally coupling.
    Type: Grant
    Filed: November 24, 1999
    Date of Patent: March 16, 2004
    Assignee: Micron Technology, Inc.
    Inventor: Joseph M. Brand
  • Patent number: 6707135
    Abstract: The semiconductor integrated circuit device comprises a planar leadframe having lead segments arranged in alternating order into first and second pluralities, the segments having their inner tips near the chip mount pad and their outer tips remote from the mount pad. The outer tips have a solderable surface. All outer tips are bent away from the leadframe plane into the direction towards the intended attachment locations on an outside substrate such that the first segment plurality forms an angle of about 70±1° from the plane and the second segment plurality forms an angle of about 75±1° (see FIG. 4). Consequently, the outer tips create a staggered lead pattern suitable for solder attachment to an outside substrate.
    Type: Grant
    Filed: November 21, 2001
    Date of Patent: March 16, 2004
    Assignee: Texas Instruments Incorporated
    Inventor: Ruben P. Madrid
  • Patent number: 6696320
    Abstract: A stacked multi-chip package includes first chip with conductive pads on both front and back sides. The front side may include a polymer layer with interconnect. A first polymer layer formed on the backside of the first chip has a cutout to receive a second chip. The first and second chip may be joined as a flip chip. A second polymer layer formed on the first polymer layer has a cutout to receive a third chip. A third polymer layer formed on the second polymer layer contains interconnect to interconnect the first, second and third chips, including the backside of the first chip. Conductive bumps on the front side of the first chip and on the polymer layers provide external I/O connection.
    Type: Grant
    Filed: September 30, 2001
    Date of Patent: February 24, 2004
    Assignee: Intel Corporation
    Inventor: Rodolfo L. Gacusan
  • Patent number: 6696747
    Abstract: A semiconductor package is disclosed that comprises a chip paddle and a semiconductor chip that has a plurality of bond pads. The semiconductor chip is located on an upper surface of the chip paddle. Leads are formed at intervals along the perimeter of the chip paddle. The leads are in electrical communication with the bond pads. The semiconductor chip, the chip paddle and the leads are encapsulated by an encapsulation material. The height of the semiconductor package of the invention is minimized by half etching the chip paddle to reduce the thickness of the chip paddle such that the thickness of the chip paddle is less than the thickness of the leads. Preferably, the chip paddle of the present invention is about 25-75% of the thickness of the leads.
    Type: Grant
    Filed: October 13, 2000
    Date of Patent: February 24, 2004
    Assignee: Amkor Technology, Inc.
    Inventors: Tae Heon Lee, Mu Hwan Seo
  • Patent number: 6692993
    Abstract: An integrated circuit (IC) package includes a mold compound, a die, and a window. The mold compound has a frame embedded within it. The frame has a coefficient of thermal expansion that is less than the mold compound. The IC package is capable of being attached to a circuit board via a mass reflow process.
    Type: Grant
    Filed: April 10, 2000
    Date of Patent: February 17, 2004
    Assignee: Intel Corporation
    Inventors: Zong-Fu Li, Kabul Sengupta, Deborah L. Thompson
  • Patent number: 6693362
    Abstract: A multichip module is provided. The multichip module comprises a rigid substrate including a core material and having an opening, a thin film fixed on an upper surface of the rigid substrate so as to be electrically connected to the rigid substrate and to close the opening, a first chip mounted on the upper surface of the thin film, and a second chip mounted on the under surface of the thin film so as to be located in the opening of the rigid substrate. The rigid substrate and the thin film form a wiring substrate having a composite structure.
    Type: Grant
    Filed: November 20, 2001
    Date of Patent: February 17, 2004
    Assignee: Fujitsu Limited
    Inventors: Kiyotaka Seyama, Hiroshi Yamada, Haruhiko Yamamoto
  • Patent number: 6680213
    Abstract: A method for fabricating contacts on semiconductor components includes the steps of testing the components, and then using test data to fabricate the contacts on only components that meet a predetermined criteria. Initially a substrate, such as a wafer or a panel, containing multiple semiconductor components, such as dice or packages, is provided. The components include integrated circuits, and component contacts in electrical communication with the integrated circuits. In a first embodiment, a ball bumper apparatus programmed with the test data forms contact bumps on dice contained on a semiconductor wafer. In a second embodiment, a ball bumper apparatus programmed with the test data forms contact bumps on packages contained on a panel. In a third embodiment, a stencil mask is patterned with openings using a laser scanner programmed with the test data, and solder is stenciled into the openings, and reflow bonded to the component contacts to form contact bumps.
    Type: Grant
    Filed: April 2, 2001
    Date of Patent: January 20, 2004
    Assignee: Micron Technology, Inc.
    Inventors: Warren M. Farnworth, Alan G. Wood, Douglas Kelly
  • Patent number: 6677229
    Abstract: The method for producing a solder bump transfer sheet of the invention includes the steps of: providing a sheet having a chromium oxide layer containing substantially no iron oxide as the outermost surface; and forming a plurality of solder bumps placed in a predetermined pattern on the chromium oxide layer.
    Type: Grant
    Filed: October 17, 2001
    Date of Patent: January 13, 2004
    Assignee: Sumitomo Special Metals Co., Ltd.
    Inventor: Masaharu Yamamoto
  • Patent number: 6660560
    Abstract: A no-flow underfill material and process for underfilling a flip chip component. The underfill material comprises at least three polymer layers. A first of the layers overlies terminals of a substrate to which the component is to be mounted. The first and second layers are substantially free of fillers, while the third layer contains a filler material to reduce its CTE. The underfill process entails placing the component so that solder terminals thereof penetrate the first, second and third layers and contact the terminals on the substrate. Because only the third layer contains filler material, penetration of the underfill material by the solder terminals is substantially unimpeded. The solder terminals are then reflowed, during which the filler material migrates into the unfilled first layer and the first, second and third layers consolidate and cure to form a single underfill layer.
    Type: Grant
    Filed: September 10, 2001
    Date of Patent: December 9, 2003
    Assignee: Delphi Technologies, Inc.
    Inventors: Arun K. Chaudhuri, Derek B. Workman, Matthew R. Walsh
  • Patent number: 6656770
    Abstract: Solder compositions are introduced to interface between an IC chip and its associated heat exchanger cover. The solder compositions have a solidus-liquidus temperature range that encompasses the IC chip operational temperature range. The solder composition has the desired property of absorbing and rejecting heat energy by changing state or phase with each temperature rise and decline that result from temperature fluctuations associated with the thermal cycles of the integrated circuit chips. The electronic module cover is a cap with a heat exchanger formed or attached as a single construction, and made of the same material as the substrate, or made with materials of compatible thermal coefficients of expansion to mitigate the effects of vertical displacement during thermal cycling.
    Type: Grant
    Filed: June 5, 2001
    Date of Patent: December 2, 2003
    Assignee: International Business Machines Corporation
    Inventors: Eugene R. Atwood, Joseph A. Benenati, Giulio DiGiacomo, Horatio Quinones
  • Patent number: 6645841
    Abstract: Selective application of solder bumps in an integrated circuit package. Solder bumps are selectively applied in a solder bump integrated circuit packaging process so that portions of a circuit can be effectively disabled. The bumps may be selectively applied either to a die or to the substrate using multiple solder masks, one for each pattern of solder bumps desired or can be otherwise applied in multiple patterns depending upon which portions of the circuitry are to be active and which are to be disabled.
    Type: Grant
    Filed: November 16, 2001
    Date of Patent: November 11, 2003
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventor: Wayne Kever
  • Patent number: 6646339
    Abstract: A semiconductor package which is improved in thinness and heat radiation and a method for making the same. The package includes a semiconductor chip electrically connected to leads of a leadframe via input and output bond pads. The leadframe may have a ground ring formed therein. The leads and semiconductor chip are at least partially encapsulated by an encapsulant. The semiconductor chip and leads have bottom surfaces which are externally exposed to improve heat radiation and reduce the thickness of the package. The package is made by placing the leadframe having leads onto adhesive tape, affixing a semiconductor chip into an open space on the leadframe, pressurizing the leadframe and chip downwardly for securement to the adhesive tape, electrically connecting input bond pads and output bond pads on the chip to the leads; at least partially encapsulating the leads and semiconductor chip; removing the tape from the bottom surfaces of the leads and chip; and cutting the leadframe to form the package.
    Type: Grant
    Filed: October 13, 2000
    Date of Patent: November 11, 2003
    Assignee: Amkor Technology, Inc.
    Inventors: Jae Hun Ku, Jae Hak Yee
  • Patent number: 6642594
    Abstract: A single chip multiple range pressure transducer device including a wafer having a plurality of simultaneously formed thinned regions. The thinned regions are separated by a fixed portion, and each have a same minimum thickness. The thinned regions have at least one different planar dimension. A plurality of piezoresistive circuits are formed on the wafer. Each of the circuits is associated with and at least partially formed above one of the thinned regions. The thinned regions deflect a different amount upon application of a common pressure thereto, whereby, when excited each of the circuits provides an output indicative the common pressure over a different operating range when the associated thinned region deflects.
    Type: Grant
    Filed: December 6, 2001
    Date of Patent: November 4, 2003
    Assignee: Kulite Semiconductor Products, Inc.
    Inventor: Anthony D. Kurtz
  • Patent number: 6642080
    Abstract: Chip-on-chip interconnections of varied characteristics, such as varied diameters, heights and/or composition, are disclosed. A first chip-on-chip interconnection on a joining plane has a first characteristic (e.g., a first height) and a second chip-on-chip interconnection on the same joining plane has a second characteristic (e.g., a second height greater than the first height). The first and second characteristics of the chip-on-chip interconnections allow for chip-on-chip connections to other packages, substrates or chips of different levels and/or compositions.
    Type: Grant
    Filed: October 18, 2000
    Date of Patent: November 4, 2003
    Assignee: International Business Machines Corporation
    Inventors: Thomas George Ference, Wayne John Howell, Edmund Juris Sprogis