Patents Examined by Ngan Ngo
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Patent number: 10109686Abstract: Disclosed is a display device comprising: a substrate comprising an active region and a non-active region; a light emitting device that emits light in the active area of the substrate; a touch sensor in the active area of the substrate that senses touch of the display device, the touch sensor including a plurality of conductive layers arranged in a stacking sequence; and a plurality of routing lines in the non-active region of the substrate that are connected to the touch sensor, each of the plurality of routing lines including a plurality of routing layers, each of the plurality of routing layers made of a same material as a corresponding one of the plurality of conductive layers included in the touch sensor, and the plurality of routing layers arranged in a same stacking sequence as the stacking sequence of the plurality of conductive layers of the touch sensor.Type: GrantFiled: February 17, 2017Date of Patent: October 23, 2018Assignee: LG Display Co., Ltd.Inventors: Jae-Young Oh, Min-Joo Kim, Jae-Won Lee, Eun-Hye Lee
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Patent number: 10109793Abstract: The present disclosure relates to a memory cell having a multi-layer bottom electrode with an insulating core that provides for good gap fill ability, and an associated method of formation. In some embodiments, the memory cell includes a bottom electrode having an insulating material surrounded by a conductive material. A dielectric data storage layer is arranged over the bottom electrode, and a top electrode is arranged over the dielectric data storage layer.Type: GrantFiled: September 26, 2016Date of Patent: October 23, 2018Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Jen-Sheng Yang, Wen-Ting Chu, Yu-Wen Liao
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Patent number: 10103220Abstract: An impurity of a second conductivity type is selectively doped in a surface of a semiconductor substrate of a first conductivity type to form doped regions. A portion of a surface of the doped regions is covered by a heat insulating film. At least a remaining portion of the surface of the doped regions is covered by an absorbing film and the doped regions are heated through the absorbing film, enabling an impurity region of the second conductivity type to be formed having two or more of the doped regions that have a same impurity concentration and differing carrier concentrations.Type: GrantFiled: February 15, 2018Date of Patent: October 16, 2018Assignee: FUJI ELECTRIC CO., LTD.Inventors: Tomonori Katano, Fumikazu Imai
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Patent number: 10103149Abstract: A semiconductor memory cell comprising an electrically floating body. A method of operating the memory cell is provided.Type: GrantFiled: October 30, 2017Date of Patent: October 16, 2018Assignee: Zeno Semiconductor, Inc.Inventors: Jin-Woo Han, Yuniarto Widjaja
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Patent number: 10103259Abstract: An interlayer insulating film is formed on a gate insulating film and a gate electrode, and the interlayer insulating film is opened forming contact holes. Next, the interlayer insulating film and regions exposed by the contact holes are covered by a titanium nitride film, and the titanium nitride film is etched to remain only at portions of the gate insulating film and the interlayer insulating film exposed in the contact holes. The interlayer insulating film and the regions exposed by the contact holes are covered by a nickel film, and after the nickel film directly contacting the interlayer insulating film is removed, the nickel film is heat treated and a nickel silicide layer is formed.Type: GrantFiled: February 20, 2018Date of Patent: October 16, 2018Assignee: FUJI ELECTRIC CO., LTD.Inventors: Masanobu Iwaya, Makoto Utsumi
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Patent number: 10096623Abstract: In a thin film transistor, an increase in off current or negative shift of the threshold voltage is prevented. In the thin film transistor, a buffer layer is provided between an oxide semiconductor layer and each of a source electrode layer and a drain electrode layer. The buffer layer includes a metal oxide layer which is an insulator or a semiconductor over a middle portion of the oxide semiconductor layer. The metal oxide layer functions as a protective layer for suppressing incorporation of impurities into the oxide semiconductor layer. Therefore, in the thin film transistor, an increase in off current or negative shift of the threshold voltage can be prevented.Type: GrantFiled: December 28, 2017Date of Patent: October 9, 2018Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Toshikazu Kondo, Hideyuki Kishida
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Patent number: 10088244Abstract: A heat sink includes a heat sink base/riser, a first fin, and a second fin. The spacing between the base/riser and the first fin and the second fin, restively, may be adjusted by rotating a threaded rod. The threaded rod includes a first threaded knurl that is engaged with the first fin and a second threaded knurl that is engaged with the second fin. The thread pitch of the first threaded knurl and the second threaded knurl may differ. For example, the pitch of the first threaded knurl may be smaller than the pitch of the second threaded knurl if the first fin is located nearest the heat sink base/riser relative to the second fin. The spacing of the heat sink fins may be adjusted based upon the current operating conditions of the electronic device to maintain an optimal temperature of a heat generating device during device operation.Type: GrantFiled: November 1, 2017Date of Patent: October 2, 2018Assignee: International Business Machines CorporationInventors: Paul F. Bodenweber, Kamal K. Sikka
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Patent number: 10083932Abstract: A method of forming a package on package, semiconductor package arrangement is described. In one aspect, solder bumps on a lower surface of a first grid array package substrate are fused to corresponding unencapsulated solder bumps on an upper surface of a second grid array package substrate. The fused solder bumps form solder joints that electrically connect the first and second packages. The height of the resulting solder joints is greater than a height of a die that is flip chip mounted to the second substrate such that the first substrate does not contact any portion of the second package and an air gap is formed that separates the second die from the first package. Corresponding PoP packages structures are also described.Type: GrantFiled: January 17, 2014Date of Patent: September 25, 2018Assignee: NVIDIA CorporationInventor: Ernesto A. Opiniano
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Patent number: 10083965Abstract: The semiconductor device includes a substrate comprising first and second regions, in the first region, first and second gate electrodes formed parallel to each other on the substrate, and being spaced apart from each other by a first distance, in the second region, third and fourth gate electrodes formed parallel to each other on the substrate, and being spaced apart from each other by a second distance which is greater than the first distance, in the first region, a first recess formed on the substrate between the first and second gate electrodes, in the second region, a second recess formed on the substrate between the third and fourth gate electrodes, a first epitaxial source/drain filling the first recess and a second epitaxial source/drain filling the second recess, wherein an uppermost portion of an upper surface of the first epitaxial source/drain is higher than an uppermost portion of an upper surface of the second epitaxial source/drain.Type: GrantFiled: December 21, 2017Date of Patent: September 25, 2018Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Ki Hwan Kim, Gi Gwan Park, Jung Gun You, Dong Suk Shin, Hyun Yul Choi
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Patent number: 10074788Abstract: Disclosed herein are a light emitting device package, a backlight unit, an illumination apparatus, and a method of manufacturing a light emitting device package capable of being used for a display application or an illumination application.Type: GrantFiled: October 24, 2017Date of Patent: September 11, 2018Assignee: LUMENS CO., LTD.Inventors: Seung-Hyun Oh, Sung-Sik Jo, Jung-A Lim, Sung-Yole Yun, Ji-Yeon Lee, Bo-Young Kim
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Patent number: 10068957Abstract: A display apparatus includes a substrate, a plurality of pixel electrodes disposed over the substrate, first metal patterns disposed over the plurality of pixel electrodes and between adjacent pixel electrodes, a first insulating layer disposed over the first metal patterns, second metal patterns disposed over the first insulating layer, in which each second metal pattern is electrically connected to one of the first metal patterns through a contact hole in the first insulating layer, and a light-blocking layer covering the second metal patterns and including first openings respectively corresponding to one of the plurality of pixel electrodes, in which each of the first openings exposes a portion of the first insulating layer.Type: GrantFiled: February 23, 2017Date of Patent: September 4, 2018Assignee: SAMSUNG DISPLAY CO., LTD.Inventors: Youngdae Kim, Taewook Kang
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Patent number: 10062611Abstract: Encapsulated semiconductor packages and methods of production thereof. As a non-limiting example, a semiconductor package may be produced by partially dicing a wafer, molding the partially diced wafer, and completely dicing the molded and partially diced wafer.Type: GrantFiled: August 22, 2017Date of Patent: August 28, 2018Assignee: Amkor Technology, Inc.Inventors: Bora Baloglu, Curtis Zwenger, Ron Huemoeller
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Patent number: 10062766Abstract: A hetero-junction Schottky diode device includes a buffer layer, at least one channel layer, at least one barrier layer and a Schottky metal layer. The buffer layer is disposed on a substrate. The at least one channel layer is disposed on the buffer layer. The at least one barrier layer is disposed on the at least one channel layer. Besides, multiple strip openings are configured to penetrate through the at least one barrier layer and at least one channel layer. The Schottky metal layer is disposed on the at least one barrier layer, across the strip openings and fills in the strip openings.Type: GrantFiled: January 10, 2018Date of Patent: August 28, 2018Assignee: Nuvoton Technology CorporationInventors: Jung-Tse Tsai, Heng-Kuang Lin
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Patent number: 10064282Abstract: A multilayer structure for an electronic device having a flexible substrate film (202) for accommodating electronics (204); at least one electronic component (204) provided on said substrate film (202); and a number of conductive traces (206) provided on said substrate film (202) for electrically powering and/or connecting electronics including said at least one electronic component (204), wherein at least one preferably thermoformed cover (210) is attached to said substrate film (202) on top of said at least one electronic component (204), the at least one thermoformed cover (210) and the substrate film (202) accommodating the electronics (204) being overmolded with thermoplastic material (208). The invention also relates to a method for manufacturing a multilayer structure for an electronic device.Type: GrantFiled: May 19, 2016Date of Patent: August 28, 2018Assignee: TACTOTEK OYInventors: Mikko Heikkinen, Jarmo Sääski, Jarkko Torvinen
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Patent number: 10043663Abstract: A heteroepitaxially grown structure includes a substrate and a mask including a high aspect ratio trench formed on the substrate. A cavity is formed in the substrate having a shape with one or more surfaces and including a resistive neck region at an opening to the trench. A heteroepitaxially grown material is formed on the substrate and includes a first region in or near the cavity and a second region outside the first region wherein the second region contains fewer defects than the first region.Type: GrantFiled: December 30, 2016Date of Patent: August 7, 2018Assignee: International Business Machines CorporationInventors: Cheng-Wei Cheng, David L. Rath, Devendra K. Sadana, Kuen-Ting Shiu, Brent A. Wacaser
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Patent number: 10043846Abstract: A radiographic detection substrate, a manufacture method thereof, and a radiographic detection device are provided. The radiographic detection substrate includes a substrate; and a thin film transistor and a signal storage unit which are formed on the substrate; the thin film transistor includes a gate electrode, an insulating layer, an active layer, a source electrode, a drain electrode and a passivation layer which are sequentially formed on the substrate; the signal storage unit includes a storage capacitor, the storage capacitor includes a first electrode and a second electrode, the first electrode is formed on the insulating layer and lapped with the drain electrode, the second electrode is connected to a ground line; the passivation layer is formed on the source electrode, the drain electrode, the first electrode and the ground line.Type: GrantFiled: November 5, 2015Date of Patent: August 7, 2018Assignee: BOE Technology Group Co., Ltd.Inventors: Wei Guo, Xingdong Liu
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Patent number: 10043797Abstract: Techniques are disclosed for forming vertical transistor architectures. In accordance with some embodiments, a semiconductor layer is disposed over a lower interconnect layer and patterned into a plurality of vertical semiconductor bodies (e.g., nanowires and/or other three-dimensional semiconductor structures) in a regular, semi-regular, or irregular array, as desired for a given target application or end-use. Thereafter, a gate layer surrounding the active channel portion of each (or some sub-set) of the vertical semiconductor bodies is formed, followed by an upper interconnect layer, in accordance with some embodiments. During processing, a given vertical semiconductor body optionally may be removed and, in accordance with some embodiments, either: (1) blanked to provide a dummy channel; or (2) replaced with an electrically conductive plug to provide a via or other inter-layer routing.Type: GrantFiled: June 23, 2014Date of Patent: August 7, 2018Assignee: Intel CorporationInventors: Kimin Jun, Patrick Morrow
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Patent number: 10038117Abstract: A semiconductor light-emitting device comprises an epitaxial structure comprising an main light-extraction surface, a lower surface opposite to the main light-extraction surface, a side surface connecting the main light-extraction surface and the lower surface, a first portion and a second portion between the main light-extraction surface and the first portion, wherein a concentration of a doping material in the second portion is higher than that of the doping material in the first portion and, in a cross-sectional view, the second portion comprises a first width near the main light-extraction surface and second width near the lower surface, and the first width is smaller than the second width.Type: GrantFiled: September 8, 2017Date of Patent: July 31, 2018Assignee: EPISTAR CORPORATIONInventors: Hsin-Chih Chiu, Shih-I Chen, You-Hsien Chang, Hao-Min Ku, Ching-Yuan Tsai, Kuan-Chih Kuo, Chih-Hung Hsiao, Rong-Ren Lee
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Patent number: 10037897Abstract: A semiconductor package includes a first semiconductor element, an insulating layer, and a second semiconductor element. The first semiconductor element includes at least one conductive layer and at least one via layer. The insulating layer is positioned above the first semiconductor device and includes at least one through insulator via (TIV) extending from a first side of the insulating layer to a second side of the insulating layer. The at least one TIV has a conductive core including a copper-containing material. The second semiconductor element is positioned above the insulating layer and includes at least one conductive layer and at least one via layer. The at least one TIV couples the at least one via layer of the first semiconductor element to the at least one via layer of the second semiconductor element.Type: GrantFiled: February 14, 2017Date of Patent: July 31, 2018Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Feng-Wei Kuo, Wen-Shiang Liao
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Patent number: 10037996Abstract: A semiconductor device includes a substrate, a bit line structure on the substrate, a first contact structure on a sidewall of the bit line structure, a second contact structure on the bit line structure and spaced apart from the first contact structure across the bit line structure, and an insulation pattern between the bit line structure and the first contact structure. The second contact structure covers at least a portion of a top surface of the bit line structure. The insulation pattern comprises a protrusion that protrudes from a sidewall of the insulation pattern that immediately adjacent to the bit line structure. The protrusion protrudes in a first direction parallel to a top surface of the substrate.Type: GrantFiled: July 11, 2017Date of Patent: July 31, 2018Assignee: Samsung Electronics Co., Ltd.Inventors: Daeik Kim, Bong-Soo Kim, Jemin Park, Yoosang Hwang