Abstract: A memory array of PROM, EPROM or EEPROM cells has each cell formed in a trench of a thick oxide layer deposited on a silicon substrate, in a manner that a significant portion of opposing areas of the floating gate and control gate of each cell which provide capacitive coupling between them are formed vertically. This allows the density of the array to be increased since the amount of semiconductor substrate area occupied by each cell is decreased without having to sacrifice the amount or quality of the capacitive coupling. Further, a technique of forming capacitive coupling between the floating gate and an erase gate in a flash EEPROM array cell with improved endurance is disclosed.

Abstract: An electronic switch, in particularly a transistor, has at least one barrier layer extending between regions of different doping concentrations within a semiconductor and is characterized in that the barrier layer has at least one voltage limiting zone (Z) having a radius of curvature (R) less than or at most equal to the diffusion depth (x.sub.JB) of the diffused junction.

Abstract: Integrated semiconductor-on-insulator (SOI) sensors and circuits which are electrostatically bonded to a support substrate, such as glass or an oxidized silicon wafer, are disclosed. The SOI sensors and SOI circuits are both formed using a novel fabrication process which allows multiple preformed and pretested integrated circuits on a silicon wafer to be electrostatically bonded to the support substrate without exposing the sensitive active regions of the electronic devices therein to a damaging electric field. The process includes forming a composite bonding structure on top of the integrated circuits prior to the bonding step. This composite structure includes a conductive layer dielectrically isolated from the circuit devices and electrically connected to the silicon wafer, which is spaced form but laterally overlaps at least the active semiconductive regions of the circuit devices.

Abstract: A mesa-type PIN diode and method for making same are disclosed. A diode made according to the present invention includes a junction formed in the top surface of the mesa-shaped structure, having an area that is less than (and preferrably, approximately half) the area of the top surface. A highly-doped, N-type conducting layer is formed in the side-walls of the mesa-shaped structure. The resulting diode is subject to greatly reduced charge carrier recombination effects and suffers from much less carrier-to-carrier scattering than conventional diodes. Thus, a diode made according to the present invention is capable of achieving much higher stored charge, lower resistance, lower capacitance, better switching characteristics, and lower power consumption than one made according to the prior art. Particular utility is found, inter alia, in the areas of high-frequency microwave and monolithic circuits.

Abstract: The semiconductor image sensor element comprises a transistor gate potential well 102, a virtual potential well 100 adjacent the transistor gate potential well 102, a clear gate barrier 104 adjacent the virtual potential well 100, a clear drain 30 adjacent the clear gate barrier 104, and a charge sensor 28 for sensing charge levels in the transistor gate potential well 102. The charge levels are responsive to light incident on the device. Charge is stored in the virtual potential well 100 during charge integration. After charge integration, the charge is transferred into the transistor gate potential well 102 from the virtual potential well 100 for charge detection by the charge sensor 28. After charge detection, the charge is transferred from the transistor potential well 102 to the clear drain 30.

Abstract: The light gathering capability or quantum efficiency of a charge-coupled device is improved by the configuration of the multi-phase gate structure to leave large surface areas of the semiconductor substrate uncovered. Each of the electrodes of the multi-phase gate structure is configured as a series of shallow H-shaped geometries, only the vertical elements of which overlap to ensure that multi-phase operation can be achieved.

Abstract: A trench of a buried plate type DRAM has a bottom portion wider than an opening portion. A silicon oxide film is formed on an upper portion of the side wall of the trench. An N-type impurity diffusion region is formed around the bottom portion of the trench. Impurity diffusion regions of adjacent trenches are integrally connected with each other as one portion. A first polycrystalline silicon layer is formed on the impurity diffusion region in the trench and the silicon oxide film. The polycrystalline silicon layer is coated with a laminated film consisting of a silicon nitride film and a silicon oxide film. The trench is filled with a second polycrystalline silicon layer covering the laminated film. The impurity diffusion region serves as a plate diffusion region of a capacitor, the first polycrystalline silicon layer serves as a plate electrode, the laminated film serves as a capacitor insulating film, and the second polycrystalline silicon layer serves as a storage node electrode.

Abstract: A charge coupled device according to the present invention, having an output terminal, for detecting an electric charge and for outputting a detection signal corresponding to the electric charge from the output terminal, comprises a semiconductor substrate having a main surface, further having a first, second and third regions in the main surface, both the first and second regions defining the third region therebetween, a charge supply formed in the vicinity of the first region, for supplying the electric charge to the first region, a first impurity formed in the first region, for transferring the electric charge to the third region, a floating gate electrode overlying the third region, coupled to the output terminal, for detecting the electric charge and outputting the detection signal corresponding to the electric charge from the output terminal in a first condition, for transferring the electric charge to the second region in a second condition, a transfer electrode overlying the second region, applied a c

Abstract: A gate electrode includes a first region formed in an OFF gate region and a second region formed in an ON gate region. A P-channel region is formed in the OFF gate region and an N-channel region is formed in the ON gate region to separate these gate regions. Since a P.sup.- -type channel region of low impurity concentration is formed at an end of a P-type base region in which the N-channel region is formed, the impurity concentration of the P-type base region can be increased and thus turn-off characteristic is improved.

Abstract: A semiconductor integrated circuit is provided which can have a high holding current without the penalty of a high gate current. Such a circuit includes a PNPN device and junction bipolar transistor in which a further doped region of the same conductivity type as the transistor collector region and more heavily doped than the collector region prevents the devices affecting each other. The junction bipolar transistor has a current gain of at least 10 and base-collector and base-emitter junctions with reverse breakdown voltages of at least 50 volts. A PN diode can also be used in the circuit.

Abstract: A multi-color imaging charge-coupled array comprises a plurality of photosensitive layers, each sensitive to a specific range of wavelengths as would be found in a full-color image. The various photosensitive layers are separated by boundary layers of high band-gap energy, so that charge packets formed within individual layers are insulated from charge packets formed in other layers within the same pixel. The combination of photosensitive layers and high band-gap boundary layers cause charge packets to be formed in potential wells within each pixel area of the charge-coupled array.

Abstract: A distributed threshold voltage TFT has a first FET and a second FET connected in series with the first point between the first and the second FET via a series circuit of a first capacitance and a second capacitance. The gate of the second FET is connected to the junction point between the first and the second capacitance and to the gate of the first FET via a non-linear resistance with a low R.sub.on and a high R.sup.off. Leakage currents can be kept very low in this DTV FET without an extra external voltage and/or without extra doping.

Abstract: There is disclosed a solid-state image sensor comprising: photo-detecting devices arranged in a matrix structure for receiving external light signals; vertical charge transfer device interposed between the columns of said photo-detecting device for vertically transferring the charges produced from said photo-detecting device according to external control signal; first horizontal charge transfer device for horizontally transferring the charges coming out of said vertical charge transfer device according to external control signal; output control device for controlling the charges flowing from said first horizontal charge transfer device to said output device; second horizontal charge transfer device for transferring the output charges of said first horizontal charge transfer device controlled by said output control device to said vertical charge transfer device according to external control signal; and a feedback line for connecting the output of said first horizontal charge transfer device to the input of sai

Abstract: A memory cell array (50) of a DRAM has a so-called divided bit line structure including two regions (50a and 50) divided from each other. One bit line (24) of a bit line pair is connected to a predetermined memory cell in a first memory cell array block (50a) and is kept in unloaded state in a second memory cell array block (50b). The other bit line (25) of a bit line pair is kept in unloaded state in the first memory cell array block (50a) and is connected to a predetermined memory cell in a first memory cell array block (50b). In these structures, the load state is kept same in both bit lines of the bit line pair. In the memory cell array, four memory cells are disposed in a cross-relationship, and are connected to the bit line (24) through a contact portion (17) used in common by the four memory cells. The word lines (20a and 20b) are formed to obliquely cross the bit lines and to extend perpendicularly to each other. Capacitors (3) in the memory cells have portions extended over the word lines.

Abstract: A groove, which runs vertically and horizontally, is formed in a substrate, thereby a plurality of silicon pillars are formed in a matrix manner. A field oxidation film is formed on the central portion of the groove. A drain diffusion layer is formed on the upper portion of each silicon pillar, and a source diffusion layer is formed on the bottom portion of the groove. A gate electrode, serving as a word line, a storage node contacting the source diffusion layer, and a cell plate are sequentially buried to enclose the surroundings of each silicon pillar, and a bit line is formed in an uppermost layer, thereby a DRAM cell array is structured.

Abstract: A dynamic random access memory includes a first conductivity type semiconductor substrate (40), a plurality of word lines (1a, 1b, 1c, 1d), a plurality of bit lines (2a, 2b) and a plurality of memory cells (3). The memory cells (3) are provided at the intersections between the word lines (1a, 1b, 1c, 1d) and the bit lines (2a, 2b). Each of the memory cells (3) includes a pair of impurity regions (6a, 6b) of a second conductivity type, a gate electrode (8) connected to the word line (1a, 1b, 1c, 1d), a storage node (9) and a cell plate (11). A capacitor (5) including the storage node (9) and the cell plate (11) is located above the bit lines (2a, 2b). The storage node (9) is formed to extend from a bottom surface to a side surface of a hole (Ct1, Ct2) formed in an insulator layer (14a, 14b) so as to extend to a surface of one impurity region (6a). The cell plate (11) is formed to interpose the storage node (9) between two layers thereof along the bottom surface and the side surface of the hole (Ct1, Ct2).

Abstract: A BiMOS integrated circuit device comprises a bipolar transistor and at least one MOSFET. The collector and emitter of the bipolar transistor are connected to a high potential source and a low potential source, respectively. The MOSFET has two gate electrodes, a source, and a drain. The source is connected to the high potential source, and the drain is the base of the bipolar transistor by a diffusion layer. The diffusion layer is located between the gate electrodes, and serves as both the base of the bipolar transistor and the drain of the MOSFET. Therefore, the MOSFET has a great channel width, and a large current can be supplied to the base of the bipolar transistor. In other words, the MOSFET has a great driving capability, and the bipolar transistor has a high amplification factor.

Abstract: The structure and method of this invention provide, for example, electrical isolation between active elements in adjacent rows and/or columns of an integrated circuit by use of a self-aligned field-plate conductor formed over and insulated from the substrate regions that are bounded by the channel regions of field-effect transistors in adjacent rows and that are bounded by the bitlines forming those transistors in a column. The field-plate conductor is formed, for example, in a strip that extends over the isolation areas and thermal insulator regions between row lines of the memory cell array. The field-plate conductor strip is connected to a voltage supply that has a potential with respect to the potential of the semiconductor substrate which causes the isolation areas to be nonconductive. Component density may be increased over that of prior-art structures and methods.

Abstract: A conductivity modulation type MISFET, and a control circuit thereof are provided. A semiconductor device 1 comprises a conductivity modulation type MOSFET 1a and a built-in MOSFET 1b which is designed to control a source electrode 12a and a control electrode 13 of a parasitic transistor to be in a short state or an open state, said conductivity modulation type MOSFET 1a having a polysilicon gate 6 on an obverse surface of n.sup.- -type conductivity modulation layer 4, a p-type channel diffusion area 7, n.sup.+ -type source diffusion area 8 and a parasitic transistor control electrode 13 conductively connected to the p-type channel diffusion area 7 through a p.sup.+ -type contact area 9.

Abstract: A semiconductor memory device having a non-volatile memory transistor and a selection transistor formed near the non-volatile memory transistor. The channel region surface of the memory transistor is formed to have the same conductivity type with a lower density than the channel region surface of the selection transistor or opposite conductivity type so that the characteristic of the memory transistor shifts to the negative side resulting in a sufficient read margin for an erased cell even at a control voltage of 0.