Abstract: A method comprises receiving an integrated circuit (IC) design file and determining, by one or more processors, dose information from the IC design file. The method further comprises determining, by the one or more processors, a mask vector file from the IC design file, and converting, by the one or more processors, the dose information to a vector file format. Further, the method comprises outputting the dose information in the vector file format and the mask vector file to a mask writer device.

Abstract: Systems and methods for measuring quantum states of qubits with more than two levels are provided. A method can include, for a plurality of shuffling sequences, applying, by a quantum computer, one or more quantum gates to the one or more qubits to execute a quantum algorithm; applying, by the quantum computer, a shuffling sequence to the one or more qubits; and measuring, using a readout apparatus, the state of the one or more qubits to determine a readout state. The method can further include determining, by a classical computer or the quantum computer, an average occupation for one or more of the quantum states of the one or more qubits using the readout states for each of the shuffling sequences. The readout states can correspond to a state in a subset of the quantum states of the one or more qubits.

Abstract: A design support device includes an operation reception unit that receives an operation from a user, a program creation unit that creates a ladder program in accordance with the operation received by the operation reception unit, and a circuit block extraction unit that extracts a circuit block from the ladder program when the circuit block is formed and a predetermined condition is satisfied. The circuit block is formed by detecting that one end of a circuit including a plurality of program elements is connected to one of two power rails included in the ladder program and that another end of the circuit is connected to another one of the two power rails. Further, there is a circuit block memory that stores configuration information of the circuit block extracted by the circuit block extraction unit. There is also a notification unit.

Abstract: A non-transitory computer-readable recording medium storing a timing library creation program of causing a computer to execute processing, the processing including: extracting, from a delay variation database that stores delay variation values of gates included in circuit design data, a delay variation value, out of the delay valuation values matching to characteristics which are characteristics of one of signal paths in the circuit design data and which include a threshold voltage, a drive force, and a number of gate stages of the signal path; calculating an extended delay variation coefficient based on the extracted delay variation value and the characteristics; and creating, based on a basic timing library in which the delay variation value is not reflected and the extended delay variation coefficient, an extended timing library in which the delay variation value is reflected.

Abstract: A design tool determines features of a circuit design and applies a first model to the features. The first model indicates a predicted value of a metric based on the plurality of features. The design tool applies an explanation model to the features, and the explanation model indicates levels of contributions by the features to the predicted value of the metric, respectively. The design tool selects a feature of the plurality of features based on the respective levels of contributions and looks up a recipe associated with the feature in a database having possible features associated with recipes. The design tool processes the circuit design according to the recipe into implementation data that is suitable for making an integrated circuit (IC).

Abstract: A method and system for implementing one or more machine learning models for accelerating formulation design for a target product that includes converting an unsupervised formulation network model to a supervised formulation network model, deriving an outcome-contributory value for each of a plurality of distinct design variables of the supervised formulation network, identifying a dependency connection between each of a plurality of distinct pairs of distinct design variables, computing a strength of connection metric value for each of the plurality of distinct pairs of distinct design variables; and generating, via a graphical user interface, a graphical rendering of the supervised formulation model that may be manipulated to accelerate for design of a proposed formulation for a target physical product.

Abstract: A network of collection, charging and distribution machines collect, charge and distribute portable electrical energy storage devices (e.g., batteries, supercapacitors or ultracapacitors). To charge, the machines employ electrical current from an external source, such as the electrical grid or an electrical service of an installation location. By default, each portable electrical energy storage device is disabled from accepting a charge unless it receives authentication information from an authorized collection, charging and distribution machine, other authorized charging device, or other authorized device that transmits the authentication credentials. Also, by default, each portable electrical energy storage device is disabled from releasing energy unless it receives authentication information from an external device to which it will provide power, such as a vehicle or other authorization device.

Abstract: Disclosed are a hybrid density abrupt interface inversion method based on machine learning constraints.

Abstract: Methods, apparatus, and processor-readable storage media for an automated platform design tool are provided herein. An example method includes extracting information from a first file corresponding to a first computing design, the information including an identifier of at least one network, components associated with the identifier, and connections for each of the components; comparing the first computing design to a second computing design, wherein the comparing comprises: detecting that a second schematic file corresponding to the second computing design comprises the identifier, and determining, for at least one given component, whether the second schematic file includes a matching component based on the set of connections for the at least one given component; determining differences between the first computing design and the second computing design based on the results of the comparing; and initiating at least one automated action based at least in part on the one or more differences.

Abstract: A method of simulating defects in an analog circuit design includes, in part, defining a multitude of defect models, defining a defect scope associated with the defect models, and compiling, by a processor, the defect models, the defect scope, and a netlist associated with the analog circuit design. The method further includes, in part, scanning the netlist to identify a multitude of nodes to which a multitude of defects defined by the defect models and the defect scope are applied, injecting the multitude of defects at the identified nodes, and simulating the analog circuit design using the injected defects.

Abstract: Disclosed is a method for fabricating of a semiconductor device. The method includes receiving a first layout including patterns for the fabrication of the semiconductor device, performing machine learning-based process proximity correction (PPC) based on features of the patterns of the first layout to generate a second layout, and performing optical proximity correction (OPC) on the second layout to generate a third layout.

Abstract: Embodiments include herein are directed towards a system and method for estimating glitch power associated with an emulation process is provided. Embodiments may include accessing, using a processor, information associated with an electronic design database and generating cycle accurate waveform information at each node of a netlist based upon, at least in part, a portion of the electronic design database. Embodiments may further include generating a probability-based model for a plurality of inputs associated with the netlist and determining one or more partial glitch transitions from each probability-based model. Embodiments may also include combining the one or more partial glitch transitions with the cycle accurate waveform information to obtain a glitch power estimation.

Abstract: A rechargeable battery kiosk can dynamically alter a charging rate of one or more rechargeable batteries housed within the rechargeable battery kiosk to increase a probability that the rechargeable battery kiosk has an ample supply of fully charged, or mostly fully charged, rechargeable batteries based on an anticipated usage data for the rechargeable battery kiosk.

Abstract: The present disclosure provides systems and methods for scalable and parallel computation of hierarchical cascading in finite element method (FEM) simulations of surface acoustic wave (SAW) devices. Different computing units of a cluster or cloud service may be assigned to independently model different core blocks or combinations of core blocks for iterative cascading to generate a model of the SAW devices. Similarly, frequency ranges may independently be assigned to computing units for modeling and analysis of devices, drastically speeding up computation.

Abstract: A charging system can include provisions for providing power to various systems or components associated with the article of footwear. A charging system may include a charging unit with one or more components configured for use with one or more articles of footwear, where the articles of footwear can include different sizes. The components can be magnetically joined to the article in some cases. Upon connection with a power source, the article may be configured to unlace automatically. In some cases, the charging system can be used to facilitate the transfer of power to components in an automated tensioning system.

Abstract: Methods, systems, and devices that support fuseload architectures for system-on-chip (SoC) reconfiguration and repurposing are described. Trim data may be loaded from fuses to registers on a die based on a fuse header. For example, a set of registers coupled with a set of fuses on the die may be identified, where the set of fuses may store trim data to be copied to the registers as part of a fuseload procedure. In such cases, one or more fuse headers may be identified within the trim data, and each fuse header may correspond to a fuse group that includes a subset of fuses. Based on one or more subfields within a fuse header, a mapping between fuse addresses and register addresses may be determined, and the trim data from each fuse group may be copied into a set of registers based on the mapping.

Abstract: A floating body SRAM cell that is readily scalable for selection by a memory compiler for making memory arrays is provided. A method of selecting a floating body SRAM cell by a memory compiler for use in array design is provided.

Abstract: An integrated circuit includes a first and a set of conductive traces, and a first conductive feature. The second set of conductive traces includes a first conductive trace of the second set of conductive traces corresponding to a gate terminal of a first p-type transistor, and a second conductive trace of the second set of conductive traces corresponding to a gate terminal of a first n-type transistor. The first conductive feature corresponds to at least a first contact of a first dummy transistor. The first conductive trace of the second set of conductive traces is electrically coupled to the second conductive trace of the second set of conductive traces by at least the first conductive feature. The first n-type transistor being part of a first transmission gate. The first p-type transistor being part of a second transmission gate.

Abstract: A computing system may include a shadow feature model training engine configured to access a set of integrated circuit (IC) layouts and capacitance values determined for components of the set of IC layouts. The shadow feature model training engine may construct shadow feature training data for the set of IC layouts, including by extracting shadow features for components of the set of IC layouts, combine extracted shadow features and determined capacitance values to form the shadow feature training data, and may further train a machine-learning (ML) model with the shadow feature training data. The computing system may also include a shadow feature application engine configured to extract shadow features for components of an input IC layout and determine capacitance values for the input IC layout via the trained ML model.

Abstract: Embodiments herein include detecting a transformation in a circuit layout before clock tree synthesis is performed, and in response, estimating a latency offset, relative to a global latency value, for a clock pin in a clock gate circuit. Moreover, the embodiments includes determining, based on the latency offset, a timing constraint for combinational logic configured to generate an enable signal for the clock gate circuit and adjusting the circuit layout based on the timing constraint to affect when the combinational logic generates the enable signal.