Abstract: A display apparatus and a method of manufacturing the same are disclosed. The display apparatus includes at least one light emitting diode chip, a conductive portion disposed under the light emitting diode chip and coupled to the light emitting diode chip, and an insulating material surrounding the conductive portion. The conductive portion includes a first conductive portion and a second conductive portion, and the insulating material is formed to expose at least a portion of the upper surfaces of the first conductive portion and the second conductive portion.

Abstract: The present disclosure discloses a method of fabricating a semiconductor layout comprising the following steps. A layout is provided, and the layout includes a plurality of connection patterns. The connection patterns are decomposed to a plurality of first connection patterns and a plurality of second connection patterns alternatively arranged with each other. An optical proximity correction process is performed on the first connection patterns and the second connection patterns to form a plurality of third connection patterns and a plurality of fourth connection patterns, wherein at least a portion of the third connection patterns is overlapped with the fourth connection patterns. The third connection patterns and the fourth connection patterns are outputted to form photomasks. Accordingly, the quality of the photomask may be improved, and the photomask may therefore include more accurate patterns and contours. The present disclosure also provides a method of fabricating a semiconductor structure.

Abstract: A method for generalizing an algorithm configured to synthesize a diagonal product of Pauli rotations to synthesize a product of Pauli rotations comprising X, Y and Z rotations, the method comprising: Providing a table of p number of rows and m number of columns, where p is a number of qubits and m a number of rotations in the quantum circuit, and where the table comprises X, Y, Z or I entry corresponding to the respective rotations of the qbits; Determining a pivot row, and recursively, until all rotations of the product of Pauli rotations are 1-qubit rotations: Determine a target row, Conjugate the target row with the pivot row by insertion of predetermined quantum gates on the qubits corresponding to the target row and/or pivot row by calling, at each recursive call, entries of the same type of the pivot row and by always calling first the identity entry.

Abstract: A novel wiring layout design method is provided. A wiring layout in which a starting terminal group and an end terminal group are electrically connected to each other is generated using layout information and a netlist. In the case where the wiring layout satisfies a design rule, a wiring resistance and a parasitic capacitance of the wiring layout are extracted. The layout information is updated using Q learning and a new wiring layout is generated. In the Q learning, a positive reward is given when the values of the wiring resistance and the parasitic capacitance decrease, and a weight of the neural network is updated in accordance with the reward. In the case where the new wiring layout satisfies the design rule, a wiring resistance and a parasitic capacitance of the new wiring layout are extracted. In the case where the change rate of the wiring resistance and the parasitic capacitance is high, the layout information is updated using the Q learning.

Abstract: An LCS orchestrator device/expansion device secondary circuit board system includes a secondary circuit board having an orchestrator connector subsystem connected to an orchestrator processing system that performs orchestration for an LCS. A primary connector on the secondary circuit board connects to a host processing system that provides an operating system for LCS, and is coupled via the secondary circuit board to a first orchestrator connector in the orchestrator connector subsystem to provide an orchestrator/host coupling used by the orchestrator processing system to provide a host endpoint to the host processing system.

Abstract: A battery cell. The battery cell incluedes a first terminal contact and a second terminal contact, an energy storage unit, a first transistor, a sensor system that is set up to acquire a state parameter of the battery cell, and a control circuit. A first pole of the energy storage unit is coupled to the first terminal contact, and a second pole of the energy storage unit is coupled to the second terminal contact. The first transistor is connected between the first terminal contact and the second terminal contact in series with the energy storage unit. The he control circuit is set up to control a switching process of the first transistor, the control circuit controlling the first transistor based on the acquired state parameter in order to control a charge current or a discharge current of the energy storage unit.

Abstract: Various embodiments provide for port generation for a circuit design based on layout connectivity information, which can be used as part of an automatic or a semi-automatic process of an electronic design automation (EDA) system. For instance, various embodiments access connectivity information for one or more networks of a circuit design, and use the connectivity information to identify pins of signal networks as positive connections for ports, and geometric shapes on references networks as candidates for negative connections for ports.

Abstract: A system and method for creating layout for standard cells are described. In various implementations, a semiconductor fabrication process (or process) forms a power signal route in a same metal zero track reserved for power rails. The process forms a contact layer with inserted spacing underneath the power signal route. Along the track, this contact layer has physical contact with the power signal route with a first distance greater than a width of any signal route in any metal layer orthogonal to the power signal route, and has no physical contact with the power signal route with a second distance greater than the width. One or more signal routes in the local interconnect layer are routed through this spacing. Without this spacing, signals would be routed through this area using the metal one layer, which increases signal congestion.

Abstract: Disclosed is a method for fabricating of a semiconductor device. The method includes receiving a first layout including patterns for the fabrication of the semiconductor device, performing machine learning-based process proximity correction (PPC) based on features of the patterns of the first layout to generate a second layout, and performing optical proximity correction (OPC) on the second layout to generate a third layout.

Abstract: A method, system and product comprising: obtaining a gate-level representation of a quantum circuit, wherein the gate-level representation comprises a set of quantum gates defining operations on a set of qubits, wherein the gate-level representation comprises a gate-level implementation of a functional block of a functional-level representation of the quantum circuit, wherein the functional block defines an operation of the quantum circuit over at least two cycles; obtaining metadata from a functional-level processing component, wherein the metadata comprise an artifact associated with the gate-level implementation of the functional block; and compiling the gate-level representation of the quantum circuit, wherein said compiling is performed based on the metadata.

Abstract: A circuit system including a first IC chip arranged in a first voltage region on a circuit board, and a second IC chip arranged in a second voltage region on the circuit board, each of the first IC chip and the second IC chip including a data communication unit to wirelessly transmit/receive data and a power transmission/reception unit to wirelessly transmit/receive power. The first IC chip and the second IC chip wirelessly transfer data and power to each other in an insulated state between the first voltage region and the second voltage region.

Abstract: A multi-level power cell pack switching circuitry having a plurality of first level cell circuits, and additional plurality of cell circuits of consecutively progressing levels, with switching and control configured to facilitate dynamically changing serial and/or parallel connections between cells and cell circuits.

Abstract: This invention enables Electric Vehicle Service Equipments to control external electrical loads, such as water heaters. The parallel electric energy demand of the external load augments the remotely controllable energy demand for charging the vehicle creating a larger controllable demand than for charging the vehicle only. This larger demand is useful in responding to requests for ancillary service from the grid and can increase the revenue for regulation services.

Abstract: A computer-implemented method for integrated circuit routing is described. The computer-implemented method comprising receiving a description of interconnected terminals of an integrated circuit with a wiring route electrically coupling the interconnected terminals and configuring a simulated environment defined via a plurality of voxels based on the description. The individual voxels included in the plurality of voxels each correspond to a spatial representation for a corresponding region of a layout associated with the integrated circuit. The computer-implemented method further includes determining local contributions of the individual voxels to a characteristic metric of the integrated circuit based on an electromagnetic simulation of the integrated circuit and revising the wiring route based on the local contributions of the individual voxels.

Abstract: Various implementations described herein refer to a device having an integrated circuit with multiple tiers including a first tier and a second tier that are arranged vertically in a stacked configuration. The first tier may have first functional components, and the second tier may have second functional components. The device may have a three-dimensional (3D) connection within the first tier that allows for synchronous signaling between the first functional components and the second functional components for reducing latency between the multiple tiers including the first tier and the second tier.

Abstract: A floating body SRAM cell that is readily scalable for selection by a memory compiler for making memory arrays is provided. A method of selecting a floating body SRAM cell by a memory compiler for use in array design is provided.

Abstract: A post-routing path delay prediction method for a digital integrated circuit is provided. First, physical design and static timing analysis are performed on a circuit by a commercial physical design tool and a static timing analysis tool, timing and physical information of a path is extracted before routing of the circuit to be used as input features of a prediction model, then the timing and physical correlation of all stages of cells in the path is captured by a transformer network, a predicted post-routing path delay is calibrated by a residual prediction structure, and finally, a final predicted post-routing path delay is output.

Abstract: A method for the exchange of electrical energy between at least two moving, electrically powered vehicles, comprising the steps: providing a first and a second electrically powered vehicle, having a respective electrical energy store, the energy store of the first and the second vehicle can emit or receive electrical energy, and the first and second vehicles move or are to be moved along a first or second route; changing the first and second routes in such a way that both changed routes coincide along a route section; steering the first and second vehicle along the changed first and second route in such a way that both the vehicles move along the coinciding route section at a distance to one another that is smaller than a predefined maximum distance; and transferring electrical energy from the energy store of the first vehicle to the energy store of the second vehicle.

Abstract: A method of routing a clock tree including a plurality of clock nets of an integrated circuit, where each of the plurality of clock nets includes at least one clock repeater, includes determining a level of a clock net of the plurality of clock nets based on a number of clock gating cells that a clock signal passes through until the clock net receives the clock signal from a clock source and routing a plurality of conductive lines in each of the plurality of clock nets by applying different routing rules to clock nets having different levels based on the determined level. Each of the plurality of clock nets is configured to transfer the clock signal to a plurality of synchronous elements or another clock net. The plurality of synchronous elements operate in synchronization with the clock signal and are included in the integrated circuit.

Abstract: A lithographic process is performed on a set of semiconductor substrates consisting of a plurality of substrates. As part of the process, the set of substrates is partitioned into a number of subsets. The partitioning may be based on a set of characteristics associated with a first layer on the substrates. A fingerprint of a performance parameter is then determined for at least one substrate of the set of substrates. Under some circumstances, the fingerprint is determined for one substrate of each subset of substrates. The fingerprint is associated with at least the first layer. A correction for the performance parameter associated with an application of a subsequent layer is then derived, the derivation being based on the determined fingerprint and the partitioning of the set of substrates.