Abstract: Disclosed are a hybrid density abrupt interface inversion method based on machine learning constraints.

Abstract: Methods, apparatus, and processor-readable storage media for an automated platform design tool are provided herein. An example method includes extracting information from a first file corresponding to a first computing design, the information including an identifier of at least one network, components associated with the identifier, and connections for each of the components; comparing the first computing design to a second computing design, wherein the comparing comprises: detecting that a second schematic file corresponding to the second computing design comprises the identifier, and determining, for at least one given component, whether the second schematic file includes a matching component based on the set of connections for the at least one given component; determining differences between the first computing design and the second computing design based on the results of the comparing; and initiating at least one automated action based at least in part on the one or more differences.

Abstract: Disclosed is a method for fabricating of a semiconductor device. The method includes receiving a first layout including patterns for the fabrication of the semiconductor device, performing machine learning-based process proximity correction (PPC) based on features of the patterns of the first layout to generate a second layout, and performing optical proximity correction (OPC) on the second layout to generate a third layout.

Abstract: A method of simulating defects in an analog circuit design includes, in part, defining a multitude of defect models, defining a defect scope associated with the defect models, and compiling, by a processor, the defect models, the defect scope, and a netlist associated with the analog circuit design. The method further includes, in part, scanning the netlist to identify a multitude of nodes to which a multitude of defects defined by the defect models and the defect scope are applied, injecting the multitude of defects at the identified nodes, and simulating the analog circuit design using the injected defects.

Abstract: Embodiments include herein are directed towards a system and method for estimating glitch power associated with an emulation process is provided. Embodiments may include accessing, using a processor, information associated with an electronic design database and generating cycle accurate waveform information at each node of a netlist based upon, at least in part, a portion of the electronic design database. Embodiments may further include generating a probability-based model for a plurality of inputs associated with the netlist and determining one or more partial glitch transitions from each probability-based model. Embodiments may also include combining the one or more partial glitch transitions with the cycle accurate waveform information to obtain a glitch power estimation.

Abstract: A rechargeable battery kiosk can dynamically alter a charging rate of one or more rechargeable batteries housed within the rechargeable battery kiosk to increase a probability that the rechargeable battery kiosk has an ample supply of fully charged, or mostly fully charged, rechargeable batteries based on an anticipated usage data for the rechargeable battery kiosk.

Abstract: The present disclosure provides systems and methods for scalable and parallel computation of hierarchical cascading in finite element method (FEM) simulations of surface acoustic wave (SAW) devices. Different computing units of a cluster or cloud service may be assigned to independently model different core blocks or combinations of core blocks for iterative cascading to generate a model of the SAW devices. Similarly, frequency ranges may independently be assigned to computing units for modeling and analysis of devices, drastically speeding up computation.

Abstract: A charging system can include provisions for providing power to various systems or components associated with the article of footwear. A charging system may include a charging unit with one or more components configured for use with one or more articles of footwear, where the articles of footwear can include different sizes. The components can be magnetically joined to the article in some cases. Upon connection with a power source, the article may be configured to unlace automatically. In some cases, the charging system can be used to facilitate the transfer of power to components in an automated tensioning system.

Abstract: Methods, systems, and devices that support fuseload architectures for system-on-chip (SoC) reconfiguration and repurposing are described. Trim data may be loaded from fuses to registers on a die based on a fuse header. For example, a set of registers coupled with a set of fuses on the die may be identified, where the set of fuses may store trim data to be copied to the registers as part of a fuseload procedure. In such cases, one or more fuse headers may be identified within the trim data, and each fuse header may correspond to a fuse group that includes a subset of fuses. Based on one or more subfields within a fuse header, a mapping between fuse addresses and register addresses may be determined, and the trim data from each fuse group may be copied into a set of registers based on the mapping.

Abstract: A floating body SRAM cell that is readily scalable for selection by a memory compiler for making memory arrays is provided. A method of selecting a floating body SRAM cell by a memory compiler for use in array design is provided.

Abstract: An integrated circuit includes a first and a set of conductive traces, and a first conductive feature. The second set of conductive traces includes a first conductive trace of the second set of conductive traces corresponding to a gate terminal of a first p-type transistor, and a second conductive trace of the second set of conductive traces corresponding to a gate terminal of a first n-type transistor. The first conductive feature corresponds to at least a first contact of a first dummy transistor. The first conductive trace of the second set of conductive traces is electrically coupled to the second conductive trace of the second set of conductive traces by at least the first conductive feature. The first n-type transistor being part of a first transmission gate. The first p-type transistor being part of a second transmission gate.

Abstract: A computing system may include a shadow feature model training engine configured to access a set of integrated circuit (IC) layouts and capacitance values determined for components of the set of IC layouts. The shadow feature model training engine may construct shadow feature training data for the set of IC layouts, including by extracting shadow features for components of the set of IC layouts, combine extracted shadow features and determined capacitance values to form the shadow feature training data, and may further train a machine-learning (ML) model with the shadow feature training data. The computing system may also include a shadow feature application engine configured to extract shadow features for components of an input IC layout and determine capacitance values for the input IC layout via the trained ML model.

Abstract: Embodiments herein include detecting a transformation in a circuit layout before clock tree synthesis is performed, and in response, estimating a latency offset, relative to a global latency value, for a clock pin in a clock gate circuit. Moreover, the embodiments includes determining, based on the latency offset, a timing constraint for combinational logic configured to generate an enable signal for the clock gate circuit and adjusting the circuit layout based on the timing constraint to affect when the combinational logic generates the enable signal.

Abstract: A monitoring device includes: an acquisition unit configured to acquire information regarding whether a learning model is in a first mode or in a second mode, the learning model configured to detect a state of an energy storage device; and a change unit configured to change an operation of a balancer circuit from a predetermined state in a case where the learning model is in the first mode, the balancer circuit configured to balance a voltage of the energy storage device.

Abstract: Systems and methods related to scheduling of tasks for execution in parallel based on geometric reach are described. An example method includes using a processor, processing information pertaining to a type of task to generate a plurality of areas of reach, where each of the plurality of areas of reach corresponds to a portion of a shared space. The method further includes using the processor, generating a plurality of inflated areas of reach by inflating each of the plurality of areas of reach based on a task-specific factor pertinent to the type of task. The method further includes automatically scheduling parallel execution of tasks associated with any of the plurality of inflated areas of reach satisfying a spatial constraint.

Abstract: Systems, methods, and other embodiments are associated with detecting an electric vehicle charging event. The system receives unknown time series data of usage values of electricity consumption, wherein the unknown time series data is unknown to have electric vehicle (EV) charge events. For a given account, the unknown time series data is converted into time intervals with corresponding usage values. Each time interval is encoded with a symbol from a series of symbols representing a level of electricity consumption, wherein the encoding generates an encoded consumption pattern of symbols. The system detects whether the encoded consumption pattern includes a string of high usage symbols that are similar to a known EV charge motif that represents a known EV charging event. Based on the detecting, the given account is marked as having an electric vehicle charge event or as not having an electric vehicle charge event.

Abstract: An information processing apparatus calculates a value based on the lengths of wires included in inner layers selecting the inner layers other than outermost layers and layers adjacent to the outermost layers from among a plurality of layers included in circuit data. The information processing apparatus generates training data including first layer data corresponding to the patterns of the outermost layers, second layer data corresponding to the patterns of the layers adjacent to the outermost layers, and the value based on the lengths of the wires. The information processing apparatus trains a machine learning model by using the training data.

Abstract: An equivalent input characterization waveform (EICW) is determined for a channel-connected block (CCB) located on a boundary of a cell, for a specific waveform of interest. The EICW and the specific waveform of interest produce a same timing characteristic of the CCB, but the EICW belongs to a set of waveforms on which a behavioral timing model for the multi-stage cell is based whereas the specific waveform of interest is not so limited. A timing response of the multi-stage cell is then estimated based on applying the EICW.

Abstract: A method for manufacturing a photo mask for a semiconductor device includes receiving a plurality of hotspot regions of a mask layout corresponding to the semiconductor device. The method further includes classifying the plurality of hotspot regions into two or more hotspot groups such that same or similar hotspot regions are classified into same hotspot groups. The hotspot groups includes a first hotspot group that has at least two hotspot regions. The method also includes correcting a first hotspot region of the first hotspot group to generate an enhancement of the first hotspot region and correcting other hotspot regions of the first hotspot group using the enhancement of the first hotspot region to generate enhancements of other hotspot regions of the first hotspot group.

Abstract: A software studying unit (122) calculates software processing time of each of a plurality of functions in a target source program. A data-flow graph generation unit (121) generates an inter-function data-flow graph of the plurality of functions based on the target source program. A hardware studying unit (130) calculates hardware processing time of each function and a circuit scale of each function by a high-level synthesis for the target source program. An implementation combination selection unit (140) selects, based on the software processing time of each function, the hardware processing time of each function, the circuit scale of each function, and the inter-function data-flow graph, an implementation combination of one or more functions to be implemented by software and one or more functions to be implemented by hardware.