Abstract: According to the present invention, it is possible to construct a backup configuration of a particular application data, without influencing data of another application. A management computer is coupled to a host computer on which an application operates, and to a storage apparatus that includes a plurality of volume groups each having one or more logical volumes. At least one of the logical volumes is allocated to the application. The management computer includes a volume group overlapping use determination part and a backup policy determination part. When the backup of the volume group to which one logical volume belongs is configured, the volume group overlapping use determination part determines whether there is another application that uses the volume group. The backup policy determination part determines whether there is set, for another volume group, backup policy information same as that set for the application.

Abstract: An integrated device able to simplify interconnects up to memories, able to prevent a reduction of performance due to an increase of area and longer interconnects, and able to speed up memory access. An input/output port of a processing module, memory interfaces, and memory banks are connected by connection interconnects arranged in a matrix in a first direction and a second direction above an arrangement region of a plurality of memory macros. As connection interconnects, command information interconnects and data interconnects are included. The command information interconnects are formed by private interconnects, while the data interconnects are formed by private interconnects for at least the second direction interconnects.

Abstract: A coherent attached processor proxy (CAPP) of a primary coherent system receives a memory access request specifying a target address in the primary coherent system from an attached processor (AP) external to the primary coherent system. The CAPP includes a CAPP directory of contents of a cache memory in the AP that holds copies of memory blocks belonging to a coherent address space of the primary coherent system. In response to the memory access request, the CAPP performs a first determination of a coherence state for the target address and allocates a master machine to service the memory access request in accordance with the first determination. Thereafter, during allocation of the master machine, the CAPP updates the coherence state and performs a second determination of the coherence state. The master machine services the memory access request in accordance with the second determination.

Abstract: The present application provides a memory module. The memory module includes one or more volatile memory devices, one or more non-volatile memory devices, and a data exchange controller. The data exchange controller controls data exchange between the volatile memory devices and the non-volatile memory devices.

Abstract: According to an aspect of the embodiment, a cache controller sets, when power supply capacity information is acquired at an update period, a size of a permitted area in which the writing of dirty data is permitted and a size of an inhibited area in which the writing of the dirty data is inhibited in a cache memory, according to the power supply capacity information. The cache controller stores the dirty data or read data read out from a disk array in the permitted area, or stores only the read data in the inhibited area.

Abstract: Methods, systems, and computer program products for tracking updates during memory migration. The method includes computer instructions for establishing communication from a source virtual machine to a target virtual machine, the source virtual machine including a memory. Contents of the memory on the source virtual machine are transmitted to the target virtual machine. The contents include a plurality of pages. Pages in the memory that are modified subsequent to being transmitted to the target virtual machine are tracked. The tracking includes creating a data structure having a plurality of bits corresponding to the pages in the memory, the bits indicating if the corresponding pages have been modified subsequent to being transmitted to the target virtual machine. The data structure also includes a first bit location index to identify the location of the first bit in the data structure that corresponds to a modified page.

Abstract: Various systems and methods for seeding a storage device. For example, a method involves accessing a policy that identifies a number of clients. The method then involves selecting a most recent backup image for each of the clients and copying the most recent backup images from a source storage device to a target storage device. Once a most recent backup image has been copied from the source storage device to the target storage device for each of the clients, the method switches a destination value in the policy from the source storage device to the target storage device.

Abstract: Embodiments of the invention are directed to optimizing reconstruction of operation data in volatile memory of solid-state storage subsystems. In various embodiments, operation data is stored in the volatile memory with persistent backup data of the operation data in the non-volatile memory. In one embodiment, operation data includes a superblock table that is used to identify most or all groups of blocks (superblocks) within the storage device that certain firmware components operate on. Sometimes operation data in the volatile memory is lost or corrupted due to a power interruption or system shutdown. To optimize the reconstruction of the superblock table or other similar operation data in the volatile memory, embodiments of the invention use a “snapshot entry” to identify the latest entry information, allowing the controller to quickly identify the most updated physical locations of the operation data portions and complete the reconstruction in an efficient manner.

Abstract: A one-dimensional array is allocated in an in-memory cache for each column in a set of tabular data. The data type of each one-dimensional array is set to be the same as the data type of the corresponding column in the tabular data. Once the one-dimensional arrays have been allocated in memory, a portion of the data from each column in the tabular data is stored in a corresponding one-dimensional array. The tabular data stored in the one-dimensional arrays in the cache may then be utilized to generate an on-screen display of a portion of the tabular data.

Abstract: A coherent attached processor proxy (CAPP) of a primary coherent system receives a memory access request specifying a target address in the primary coherent system from an attached processor (AP) external to the primary coherent system. The CAPP includes a CAPP directory of contents of a cache memory in the AP that holds copies of memory blocks belonging to a coherent address space of the primary coherent system. In response to the memory access request, the CAPP performs a first determination of a coherence state for the target address and allocates a master machine to service the memory access request in accordance with the first determination. Thereafter, during allocation of the master machine, the CAPP updates the coherence state and performs a second determination of the coherence state. The master machine services the memory access request in accordance with the second determination.

Abstract: In some embodiments a controller includes a memory activate pin, one or more combined memory command/address signal pins, and a selection circuit adapted to select in response to the memory activate pin as each of the one or more combined memory command/address signal pins either a memory command signal or a memory address signal. Other embodiments are described and claimed.

Abstract: A method and apparatus for monitor and mwait in a distributed cache architecture is disclosed. One embodiment includes an execution thread sending a MONITOR request for an address to a portion of a distributed cache that stores the data corresponding to that address. At the distributed cache portion the MONITOR request and an associated speculative state is recorded locally for the execution thread. The execution thread then issues an MWAIT instruction for the address. At the distributed cache portion the MWAIT and an associated wait-to-trigger state are recorded for the execution thread. When a write request matching the address is received at the distributed cache portion, a monitor-wake event is then sent to the execution thread and the associated monitor state at the distributed cache portion for that execution thread can be reset to idle.

Abstract: A data processing system having a processor and a target device processes decorated instructions (i.e. an instruction having a decoration value). A device of the data processing system such as the processor sends transactions to the target device over a system interconnect. A decorated storage notify (DSN) transaction includes an indication of an instruction operation, an address associated with the instruction operation, and a decoration value (i.e. a command to the target device to perform a function in addition to a store or a load). The transaction on the system interconnect includes an address phase and no data phase, thereby improving system bandwidth. In one form the target device (e.g. a memory with functionality in addition to storage functionality) performs a read-modify-write operation using information at a storage location of the target device.

Abstract: Techniques for performing fast timing reacquisition of read timing in a memory controller to support rank switching device are described. During operation, a memory controller receives read data for a read operation, wherein the read data includes a calibration preamble. The memory controller uses the calibration preamble to perform a fast timing reacquisition operation to compensate for a timing drift between a clock path and a data path for the read data. In particular, the memory controller performs the fast timing reacquisition by adjusting a data delay line coupled to a clock path associated with a control loop, wherein the control loop controls a data clock which is used to receive read data at the memory controller.

Abstract: According to the present invention, it is possible to construct a backup configuration of a particular application data, without influencing data of another application. A management computer is coupled to a host computer on which an application operates, and to a storage apparatus that includes a plurality of volume groups each having one or more logical volumes. At least one of the logical volumes is allocated to the application. The management computer includes a volume group overlapping use determination part and a backup policy determination part. When the backup of the volume group to which one logical volume belongs is configured, the volume group overlapping use determination part determines whether there is another application that uses the volume group. The backup policy determination part determines whether there is set, for another volume group, backup policy information same as that set for the application.

Abstract: Various systems and methods for configuring a duplication operation. For example, a method involves specifying a duplication window, a source storage device, and a target storage device. When a duplication operation is executed, data is copied from the source storage device to the target storage device during the duplication window. The method also involves calculating a predicted duplication rate, where the predicted duplication rate is an estimate of a rate at which data can be copied from the source storage device to the target storage device.

Abstract: A portable storage system. The portable storage system comprises a portable storage device having a flash memory element and a loss-prevention unit. The portable storage system further comprises Master and Slave proximity elements. One of the proximity elements is physically connected with the portable storage device, while the other is physically connected with the loss-prevention unit. The Master proximity element is configured to wirelessly determine the presence of the Slave proximity element within a predefined range.

Abstract: Disclosed is a scratch pad memory management device and a method thereof. The scratch pad memory management device divides a scratch pad memory into a plurality of unit blocks, maintains a memory allocation table corresponding to indices of the plurality of unit blocks in a main memory, and manages the scratch pad memory.

Abstract: In one embodiment, a cache memory includes a cache array including a plurality of entries for caching cache lines of data, where the plurality of entries are distributed between a first region implemented in a first memory technology and a second region implemented in a second memory technology. The cache memory further includes a cache directory of the contents of the cache array and a cache controller that controls operation of the cache memory.

Abstract: Embodiments of a memory system that communicates bidirectional data between a memory controller and a memory IC via bidirectional links using half-duplex communication are described. Each of the bidirectional links conveys write data or read data, but not both. States of routing circuits in the memory controller and the memory IC are selected for a current command being processed so that data can be selectively routed from a queue in the memory controller to a corresponding bank set in the memory IC via one of the bidirectional links, or to another queue in the memory controller from a corresponding bank set in the memory IC via another of the bidirectional links. This communication technique reduces or eliminates the turnaround delay that occurs when the memory controller transitions from receiving the read data to providing the write data, thereby eliminating gaps in the data streams on the bidirectional links.