Patents Examined by Nikolay K Yushin
  • Patent number: 10886141
    Abstract: Provided is a method of depositing tungsten, in which depositing a tungsten nucleation layer is formed by performing a unit cycle at least once, wherein the unit cycle includes an absorption step in which a first process gas is provided on a substrate such that at least a portion of the first process gas is absorbed on the substrate, a first purge step in which a purge gas is provided on the substrate to purge the first process gas which has not been absorbed on the substrate, a reaction step in which a gas containing tungsten is provided on the substrate as a second process gas to form a unit deposition film on the substrate, a second purge step in which a purge gas is provided on the substrate to purge a reaction by-product on the substrate, a processing step in which a processing gas containing a hydrogen (H) element is provided on the substrate to reduce the concentration of an impurity in the unit deposition film, and a third purge step in which a purge gas is provided on the substrate to purge the proce
    Type: Grant
    Filed: July 24, 2019
    Date of Patent: January 5, 2021
    Assignee: WONIK IPS CO., LTD.
    Inventor: Won Jun Yoon
  • Patent number: 10886499
    Abstract: A light emitting display apparatus includes a passivation layer on a thin film transistor, a light emitting diode on the passivation layer, the light emitting diode having an anode, a light emitting layer on the anode, and a cathode on the light emitting layer, and a hydrogen absorbing layer on the light emitting diode, the hydrogen absorbing layer including an inorganic material having a mass percentage of 0.08% to 50%.
    Type: Grant
    Filed: July 15, 2019
    Date of Patent: January 5, 2021
    Assignee: LG DISPLAY CO., LTD.
    Inventors: Goeun Kim, YoungHoon Shin
  • Patent number: 10879069
    Abstract: A hard mask film forming method includes preparing a substrate in which an etching target film is formed on a base. The hard mask film forming method further includes forming a hard mask film on the substrate while controlling film forming parameters such that tensile stress is set as initial film stress and the tensile stress monotonously increases from a bottom surface of the hard mask film toward an upper surface of the hard mask film.
    Type: Grant
    Filed: July 12, 2019
    Date of Patent: December 29, 2020
    Assignee: TOKYO ELECTRON LIMITED
    Inventor: Yutaka Fujino
  • Patent number: 10879289
    Abstract: A method for fabricating a semiconductor device is provided. The method includes forming a metal catalyst layer on an etching area of the semiconductor substrate; performing a wet etch process to the semiconductor substrate to etch the etching area of the semiconductor substrate under the metal catalyst layer, thereby forming a trench in the semiconductor substrate; and removing the metal catalyst layer from the semiconductor substrate after performing the wet etch process.
    Type: Grant
    Filed: July 15, 2019
    Date of Patent: December 29, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chin-Yu Lin, Keng-Ying Liao, Huai-Jen Tung, Po-Zen Chen, Su-Yu Yeh, Chia-Yun Chen, Ta-Cheng Wei
  • Patent number: 10879052
    Abstract: A method for manufacturing a semiconductor structure includes depositing a wafer in a processing chamber. Plasma is formed in the processing chamber to process the wafer. A plasma concentration over a peripheral region of the wafer is detected. A plasma distribution over the peripheral region of the wafer is adjusted according to the detected plasma concentration.
    Type: Grant
    Filed: July 24, 2019
    Date of Patent: December 29, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventor: Han-Wen Liao
  • Patent number: 10875143
    Abstract: An apparatus for CMP includes a platen, a wafer carrier retaining a semiconductor wafer during a polishing operation, a dresser configured to recondition a polishing pad disposed on the platen during the polishing operation, and a vibration-monitoring system configured to detect vibrations during the polishing operation. The vibration-monitoring system includes a first vibration sensor configured to generate a plurality of first vibration signals. An end point is triggered to the polishing when a change between the plurality of vibration signals reaches a value.
    Type: Grant
    Filed: July 24, 2019
    Date of Patent: December 29, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: James Jeng-Jyi Hwang, Jiann Lih Wu, He Hui Peng, Chi-Ming Yang
  • Patent number: 10872967
    Abstract: A manufacturing method of a semiconductor device includes the following steps. At least one mesa structure is provided. The mesa structure includes a III-V compound semiconductor layer. A passivation layer is formed on the mesa structure. A gate dielectric layer is formed on the passivation layer, and a gate electrode is formed on the gate dielectric layer. An etching process is performed to the gate dielectric layer for thinning the gate dielectric layer before the step of forming the gate electrode. The thickness of the gate dielectric layer may be modified by the etching process, and the electrical performance of the semiconductor device may be enhanced accordingly.
    Type: Grant
    Filed: July 24, 2019
    Date of Patent: December 22, 2020
    Assignee: GLC SEMICONDUCTOR GROUP (CQ) CO., LTD.
    Inventors: Yi-Chun Shih, Shun-Min Yeh
  • Patent number: 10872829
    Abstract: A thin film transistor, a display substrate and a method for repairing the same, and a display device are provided. The thin film transistor includes: an active region, a gate insulating layer disposed on a side of the active region, and a gate disposed on a side of the gate insulating layer distal to the active region, and the active region includes a first electrode contact region at one end of the active region, a second electrode contact region at the other end of the active region, and a plurality of connection regions between the first electrode contact region and the second electrode contact region, and each of the plurality of connection regions is coupled to the first electrode contact region and the second electrode contact region, and every two adjacent connection regions are provided with an opening therebetween and are spaced apart from each other by the opening.
    Type: Grant
    Filed: May 31, 2019
    Date of Patent: December 22, 2020
    Assignees: HEFEI XINSHENG OPTOELECTRONICS TECHNOLOGY CO., LTD., BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Haitao Wang, Guangyao Li, Jun Wang, Qinghe Wang, Ning Liu, Dongfang Wang
  • Patent number: 10868039
    Abstract: A manufacturing method of a semiconductor device is provided. The method includes forming a sacrificial layer with different material layers, and etching the sacrificial layer.
    Type: Grant
    Filed: July 15, 2019
    Date of Patent: December 15, 2020
    Assignee: SK hynix Inc.
    Inventor: Byung Woo Kang
  • Patent number: 10859878
    Abstract: According to one embodiment, a display device comprises a first substrate, a second substrate opposed to the first substrate and including a first organic film, a first convex portion extending in a first direction, a second convex portion extending in a second direction intersecting the first direction, and a third convex portion aligned with the first convex portion in the second direction and extending in the first direction, and a sealing member located in a second area around a first area in which an image is displayed, wherein the first convex portion, the second convex portion and the third convex portion are located between the first organic film and the sealing member.
    Type: Grant
    Filed: August 27, 2019
    Date of Patent: December 8, 2020
    Assignee: JAPAN DISPLAY INC.
    Inventors: Tomokazu Ishikawa, Masaru Nakakomi
  • Patent number: 10861694
    Abstract: A method of manufacturing an insulation layer on silicon carbide includes first preparing a surface of the silicon carbide, then forming a first part of the insulation layer on the surface at a temperature lower than 400° Celsius. Finally, a second part of the insulation layer is formed by depositing a dielectric film on the first part. The surface of the silicon carbide is illuminated by a light at a wavelength below and/or equal to 450 nm during and/or after the formation of the first part of the insulation layer.
    Type: Grant
    Filed: December 21, 2017
    Date of Patent: December 8, 2020
    Assignee: ZF FRIEDRICHSHAFEN AG
    Inventor: Yuji Komatsu
  • Patent number: 10861978
    Abstract: A thin film transistor according to an exemplary embodiment of the present invention includes an oxide semiconductor. A source electrode and a drain electrode face each other. The source electrode and the drain electrode are positioned at two opposite sides, respectively, of the oxide semiconductor. A low conductive region is positioned between the source electrode or the drain electrode and the oxide semiconductor. An insulating layer is positioned on the oxide semiconductor and the low conductive region. A gate electrode is positioned on the insulating layer. The insulating layer covers the oxide semiconductor and the low conductive region. A carrier concentration of the low conductive region is lower than a carrier concentration of the source electrode or the drain electrode.
    Type: Grant
    Filed: December 24, 2018
    Date of Patent: December 8, 2020
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Yong Su Lee, Yoon Ho Khang, Dong Jo Kim, Hyun Jae Na, Sang Ho Park, Se Hwan Yu, Chong Sup Chang, Dae Ho Kim, Jae Neung Kim, Myoung Geun Cha, Sang Gab Kim, Yu-Gwang Jeong
  • Patent number: 10854638
    Abstract: An object is to provide a semiconductor device having a structure with which parasitic capacitance between wirings can be sufficiently reduced. An oxide insulating layer serving as a channel protective layer is formed over part of an oxide semiconductor layer overlapping with a gate electrode layer. In the same step as formation of the oxide insulating layer, an oxide insulating layer covering a peripheral portion of the oxide semiconductor layer is formed. The oxide insulating layer which covers the peripheral portion of the oxide semiconductor layer is provided to increase the distance between the gate electrode layer and a wiring layer formed above or in the periphery of the gate electrode layer, whereby parasitic capacitance is reduced.
    Type: Grant
    Filed: August 21, 2019
    Date of Patent: December 1, 2020
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Hiroki Ohara, Toshinari Sasaki, Kosei Noda, Hideaki Kuwabara
  • Patent number: 10854734
    Abstract: A manufacturing method of a semiconductor device includes the following steps. A substrate is provided. The substrate has a first side and a second side opposite to the first side. A first III-V compound layer is formed at the first side of the substrate. A drain trench and a contact trench are formed at the second side of the substrate. The drain trench extends from the second side of the substrate toward the first side of the substrate and penetrates the substrate. The contact trench extends from the second side of the substrate toward the first side of the substrate and penetrates the substrate. The drain trench and the contact trench are formed concurrently by the same process. A drain electrode is formed in the drain trench. A back contact structure is formed in the contact trench.
    Type: Grant
    Filed: July 24, 2019
    Date of Patent: December 1, 2020
    Assignee: GLC SEMICONDUCTOR GROUP (CQ) CO., LTD.
    Inventors: Yi-Chun Shih, Shun-Min Yeh
  • Patent number: 10854815
    Abstract: An apparatus for manufacturing a display apparatus includes: a chamber; a plurality of source units outside the chamber, wherein the plurality of source units which accommodate a deposition material and transform the deposition material into gas; a nozzle unit in the chamber, wherein the nozzle unit is connected to the plurality of source units and injects, into the chamber, the deposition material supplied from one of the plurality of source units; and a regulating unit between each of the plurality of source units and the nozzle unit, wherein the regulating unit interrupts the deposition material supplied from each of the plurality of source units to the nozzle unit and selectively connects the plurality of source units with the nozzle unit.
    Type: Grant
    Filed: May 30, 2019
    Date of Patent: December 1, 2020
    Assignee: Samsung Display Co., Ltd.
    Inventors: Sangjin Han, Junha Park, Eugene Kang, Dongwook Kim, Cheollae Roh, Jaewan Seol, Seongho Jeong, Myungsoo Huh, Mingyu Seo
  • Patent number: 10847858
    Abstract: A method for manufacturing a self-biased circulator includes cooling a nanocomposite material to a magnetization temperature below 200 K, applying an external magnetic field to the nanocomposite material to form a magnetic nanocomposite material, providing the magnetic nanocomposite material in a semiconductor substrate, and providing one or more metal layers over the magnetic nanocomposite material to form a circulator. By cooling and then magnetizing the nanocomposite material, a performance of the circulator may be significantly improved.
    Type: Grant
    Filed: May 30, 2019
    Date of Patent: November 24, 2020
    Assignee: Qorvo US, Inc.
    Inventors: Yu Cao, Yongjie Cui, Subrahmanyam V. Pilla
  • Patent number: 10847495
    Abstract: A bonding system includes a surface modifying apparatus, a surface hydrophilizing apparatus and a bonding apparatus. The surface modifying apparatus is configured to modify a bonding surface of a first substrate and a bonding surface of a second substrate with plasma. The surface hydrophilizing apparatus is configured to hydrophilize the modified bonding surfaces of the first substrate and the second substrate. The bonding apparatus includes a condensation suppressing gas discharge unit, and is configured to bond the hydrophilized bonding surfaces of the first substrate and the second substrate by an intermolecular force. The condensation suppressing gas discharge unit is configured to discharge a condensation suppressing gas toward a space between a peripheral portion of the bonding surface of the first substrate and a peripheral portion of the bonding surface of the second substrate facing each other.
    Type: Grant
    Filed: April 4, 2019
    Date of Patent: November 24, 2020
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Atsushi Nagata, Hiroshi Maeda, Kenji Sugakawa
  • Patent number: 10847425
    Abstract: A method for fabricating a semiconductor device includes forming a plurality of gate structures, a source/drain doped layer, a barrier layer, and a dielectric layer on a base substrate. The barrier layer covers the entire top surfaces of the plurality of gate structures. The dielectric layer covers the source/drain doped layer, the barrier layer, and the gate structures. The method further includes forming a plurality of first vias in the dielectric layer on both sides of each gate structure above the source/drain doped layer; forming a plurality of second vias on the gate structures to expose the barrier layer; performing a pre-amorphizing implantation process on the surface of the source/drain doped layer at the bottom of the first vias; removing the barrier layer at the bottom of the second vias; and forming a metal silicide layer on the surface of the source/drain doped layer through a metal silicidation process.
    Type: Grant
    Filed: July 15, 2019
    Date of Patent: November 24, 2020
    Assignees: Semiconductor Manufacturing International (Beijing) Corporation, Semiconductor Manufacturing International (Shanghai) Corporation
    Inventors: Yi Lu, Changyong Xiao, Yihui Lin, Qin Zhang, Hua Wang, Xiang Hu, Xiaona Zhu, Ying Jiang
  • Patent number: 10840081
    Abstract: A substrate liquid processing method includes immersing the substrate in a processing liquid for processing the substrate, detecting a conversion point at which a processing condition of the processing the substrate is changed, and changing the processing condition when the conversion point is detected.
    Type: Grant
    Filed: May 30, 2019
    Date of Patent: November 17, 2020
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Takumi Honda, Kazusige Sano, Hironobu Hyakutake
  • Patent number: 10840088
    Abstract: Techniques for deposition of high-density dielectric films for patterning applications are described. More particularly, a method of processing a substrate is provided. The method includes flowing a precursor-containing gas mixture into a processing volume of a processing chamber having a substrate positioned on an electrostatic chuck. The substrate is maintained at a pressure between about 0.1 mTorr and about 10 Torr. A plasma is generated at the substrate level by applying a first RF bias to the electrostatic chuck to deposit a dielectric film on the substrate. The dielectric film has a refractive index in a range of about 1.5 to about 3.
    Type: Grant
    Filed: July 15, 2019
    Date of Patent: November 17, 2020
    Assignee: Applied Materials, Inc.
    Inventors: Eswaranand Venkatasubramanian, Samuel E. Gottheim, Pramit Manna, Abhijit Basu Mallick