Patents Examined by Nikolay K Yushin
  • Patent number: 10784090
    Abstract: A plasma processing device includes a chamber; a substrate stage that supports a substrate inside the chamber; a plasma generator that generates plasma by which the substrate is processed in a space above the substrate inside the chamber; and an electromagnet. The electromagnet is provided in each of a plurality of regions, which are provided on a top of the chamber in an upper part thereof, so as to be independently movable. The plasma processing device further includes a controller configured to move the electromagnet to produce a uniform plasma density onto the substrate.
    Type: Grant
    Filed: March 1, 2019
    Date of Patent: September 22, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Takashi Ohashi
  • Patent number: 10777719
    Abstract: A base member includes a lead frame and a resin molded body in which the lead frame is embedded. The resin molded body and the lead frame define a plurality of recesses arranged in a matrix along a first direction and a second direction orthogonally crossing the first direction in a plan view. The resin molded body has a plurality of bottom surface portions each defining a part of a bottom surface of a corresponding one of the recesses, and a wall portion surrounding each of the bottom surface portions in the plan view, with an upper surface of the wall portion defining at least one a groove portion extending in the first direction or the second direction.
    Type: Grant
    Filed: April 3, 2019
    Date of Patent: September 15, 2020
    Assignee: NICHIA CORPORATION
    Inventor: Kiyoshi Kayama
  • Patent number: 10777430
    Abstract: A method includes placing an electronic die and a photonic die over a carrier, with a back surface of the electronic die and a front surface of the photonic die facing the carrier. The method further includes encapsulating the electronic die and the photonic die in an encapsulant, planarizing the encapsulant until an electrical connector of the electronic die and a conductive feature of the photonic die are revealed, and forming redistribution lines over the encapsulant. The redistribution lines electrically connect the electronic die to the photonic die. An optical coupler is attached to the photonic die. An optical fiber attached to the optical coupler is configured to optically couple to the photonic die.
    Type: Grant
    Filed: March 1, 2019
    Date of Patent: September 15, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, An-Jhih Su, Wei-Yu Chen
  • Patent number: 10763457
    Abstract: An organic light-emitting diode display device can include a substrate including first, second and third sub-pixels, each of the first, second and third sub-pixels including an emission area and a non-emission area; a driving thin film transistor in the non-emission area of each of the first, second and third sub-pixels; a light-emitting diode connected to the driving thin film transistor; a polarizer at an outer surface of the substrate, the polarizer including a reflective polarizer; and a light control pattern disposed inside of the substrate and corresponding to the non-emission area, the light control pattern being configured to change a direction of light incident on the light control pattern.
    Type: Grant
    Filed: August 12, 2019
    Date of Patent: September 1, 2020
    Assignee: LG DISPLAY CO., LTD.
    Inventors: Sung-Rae Lee, Young-Hun Jeong, Sang-Dae Han
  • Patent number: 10755989
    Abstract: A semiconductor substrate manufacturing method according to an embodiment comprises the steps of: contaminating at least one of a surface layer of a doped semiconductor substrate having a specific resistance of less than 0.1 ?·cm and a bulk layer below the surface layer with at least one metal of Fe, Cu, and Ni; performing dry oxidation at 950° C. for 30 minutes to forcibly form an oxide film on the surface of the semiconductor substrate; and assessing at least one of the presence and the degree of contamination of metal contained in at least one of the oxide film-formed surface layer and bulk layer by using a photoluminescence assessment method.
    Type: Grant
    Filed: November 28, 2017
    Date of Patent: August 25, 2020
    Assignee: SK SILTRON CO., LTD.
    Inventors: Kyung Sun Lee, Ho Chan Ham
  • Patent number: 10756259
    Abstract: The bottom-pinned spin-orbit torque (SOT) MRAM devices are fabricated to form high quality interfaces between layers including the spin-orbit torque (SOT) layer and the free layer of the magnetic tunnel junction (MTJ) by forming those layers under vacuum, without breaking vacuum in between formation of the layers. An encapsulation layer is used as an etch stop and to protect the free layer. The encapsulation layer is etched back prior to the deposition of a metal layer. The metal layer forms a plurality of metal lines that are electrically connected to two or more sides of the SOT layer and are electrically coupled to the SOT layer to transfer current through the SOT layer. The metal lines are not in contact with a top surface of the SOT layer which has a dielectric layer disposed thereon.
    Type: Grant
    Filed: March 1, 2019
    Date of Patent: August 25, 2020
    Assignee: Applied Materials, Inc.
    Inventors: Jaesoo Ahn, Chando Park, Hsin-wei Tseng, Lin Xue, Mahendra Pakala
  • Patent number: 10756159
    Abstract: Display panel and display device are provided. The display panel includes a notch region, a display region, a frame region surrounding the display region, and a first base plate. The frame region includes a first frame region and a second frame region opposite to each other. A portion of the first frame region recesses toward the display region to form the notch region. The first base plate includes an anode power bus, an anode power connection part, and anode power connection wires. The anode power wires are disposed in the display region and include first anode power wires extending along a second direction perpendicular to the first direction. At least a portion of the anode power bus is disposed in the first frame region. The anode power connection part includes a first anode power connection part to connect the anode power bus to the first anode power wires.
    Type: Grant
    Filed: July 3, 2019
    Date of Patent: August 25, 2020
    Assignee: XIAMEN TIANMA MICRO-ELECTRONICS CO., LTD.
    Inventors: Jiachang Gu, Shanfu Yuan, Tao Peng
  • Patent number: 10749055
    Abstract: A method of producing sensors includes providing a carrier plate; arranging semiconductor chips on the carrier plate, wherein the semiconductor chips include at least radiation-detecting semiconductor chips; providing radiation-transmissive optical elements on the carrier plate provided with the semiconductor chips, wherein a plurality of radiation-transmissive optical elements are provided jointly on the carrier plate provided with the semiconductor chips; and singulating the carrier plate provided with the semiconductor chips and the radiation-transmissive optical elements, thereby forming separate sensors including a section of the carrier plate, at least one radiation-detecting semiconductor chip and at least one radiation-transmissive optical element.
    Type: Grant
    Filed: October 5, 2017
    Date of Patent: August 18, 2020
    Assignee: OSRAM OLED GmbH
    Inventors: Dirk Becker, Matthias Sperl
  • Patent number: 10748783
    Abstract: The present disclosure relates to high pressure processing apparatus for semiconductor processing. The apparatus described herein include a high pressure process chamber and a containment chamber surrounding the process chamber. A high pressure fluid delivery module is in fluid communication with the high pressure process chamber and is configured to deliver a high pressure fluid to the process chamber.
    Type: Grant
    Filed: July 12, 2019
    Date of Patent: August 18, 2020
    Assignee: Applied Materials, Inc.
    Inventors: Adib M. Khan, Qiwei Liang, Sultan Malik, Srinivas D. Nemani
  • Patent number: 10748761
    Abstract: A semiconductor manufacturing apparatus includes at least one UV lamp provided at a position facing a surface of a semiconductor substrate arranged to irradiate the surface of the semiconductor substrate with UV light, and a shutter disposed between the surface of the semiconductor substrate and the at least one UV lamp and configured to block UV light emitted by the UV lamp. The shutter includes a first movable part movable in a first direction being an in-plane direction parallel to the semiconductor substrate, and a second movable part movable in a second direction being an in-plane direction perpendicular to the first direction, the second movable part being movable independently of the first movable part.
    Type: Grant
    Filed: March 1, 2019
    Date of Patent: August 18, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Akitsugu Hatazaki, Kotaro Nomura
  • Patent number: 10741581
    Abstract: A process for manufacturing a 3-dimensional memory structure includes: (a) providing one or more active layers over a planar surface of a semiconductor substrate, each active layer comprising (i) first and second semiconductor layers of a first conductivity; (ii) a dielectric layer separating the first and second semiconductor layer; and (ii) one or more sacrificial layers, at least one of sacrificial layers being adjacent the first semiconductor layer; (b) etching the active layers to create a plurality of active stacks and a first set of trenches each separating and exposing sidewalls of adjacent active stacks; (c) filling the first set of trenches by a silicon oxide; (d) patterning and etching the silicon oxide to create silicon oxide columns each abutting adjacent active stacks and to expose portions of one or more sidewalls of the active stacks; (e) removing the sacrificial layers from exposed portions of the sidewalls by isotropic etching through the exposed portions of the sidewalls of the active stack
    Type: Grant
    Filed: July 12, 2019
    Date of Patent: August 11, 2020
    Assignee: SUNRISE MEMORY CORPORATION
    Inventors: Eli Harari, Scott Brad Herner, Wu-Yi Henry Chien
  • Patent number: 10741720
    Abstract: A light emitting diode includes a square quantum well structure, the quantum well structure including III-V materials. A dielectric layer is formed on the quantum well structure. A plasmonic metal is formed on the dielectric layer and is configured to excite surface plasmons in a waveguide mode that is independent of light wavelength generated by the quantum well structure to generate light.
    Type: Grant
    Filed: February 11, 2019
    Date of Patent: August 11, 2020
    Assignee: International Business Machines Corporation
    Inventors: Yaojia Chen, Ning Li, Devendra K. Sadana, Jinghui Yang
  • Patent number: 10741567
    Abstract: A memory cell includes a select device and a capacitor electrically coupled in series with the select device. The capacitor includes two conductive capacitor electrodes having ferroelectric material there-between. The capacitor has an intrinsic current leakage path from one of the capacitor electrodes to the other through the ferroelectric material. There is a parallel current leakage path from the one capacitor electrode to the other. The parallel current leakage path is circuit-parallel the intrinsic path and of lower total resistance than the intrinsic path. Other aspects are disclosed.
    Type: Grant
    Filed: February 25, 2019
    Date of Patent: August 11, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Kamal M. Karda, Qian Tao, Durai Vishak Nirmal Ramaswamy, Haitao Liu, Kirk D. Prall, Ashonita Chavan
  • Patent number: 10734509
    Abstract: A nitride semiconductor epitaxial stack structure including: a silicon substrate; an AlN nucleation layer disposed on the silicon substrate; a buffer structure disposed on the aluminum-including nucleation layer and sequentially including a first superlattice epitaxial structure, a first GaN-based layer disposed on the first superlattice epitaxial structure, and a second superlattice epitaxial structure disposed on the first GaN based layer; a channel layer disposed on the buffer structure; and a barrier layer disposed on the channel layer; wherein the first superlattice epitaxial structure includes a first average Al composition ratio, the first GaN-based layer includes a first Al composition ratio, the_second superlattice epitaxial structure includes a second average Al composition ratio; wherein an Al composition ratio of the AlN nucleation layer?the first average Al composition ratio of the first superlattice epitaxial structure>the first Al composition ratio of the first GaN based layer>the second
    Type: Grant
    Filed: July 15, 2019
    Date of Patent: August 4, 2020
    Assignee: Epistar Corporation
    Inventors: Shang Ju Tu, Ya Yu Yang, Chia Cheng Liu, Tsung Cheng Chang
  • Patent number: 10734540
    Abstract: An optical device includes a substrate, a light receiving component, an encapsulant, a coupling layer and a light shielding layer. The light receiving component is disposed on the substrate. The encapsulant covers the light receiving component. The coupling layer is disposed on at least a portion of the encapsulant. The light shielding layer is disposed on the coupling layer.
    Type: Grant
    Filed: July 3, 2019
    Date of Patent: August 4, 2020
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventor: Jenchun Chen
  • Patent number: 10734549
    Abstract: A method of improving high-current density efficiency of an LED, said method comprising: (a) preparing a series of LEDs having decreasing defect densities, wherein each LED of said series has a peak IQE of at least 50%, and wherein each LED of said series has the same epitaxial structure; (b) determining an increase in IQEs at high-current density between at least two LEDs of said series; (c) preparing at least an additional LED of said series by reducing defect density relative to the previously obtained lowest defect density; and (d) reiterating steps (b) and (c) until said increase is at least 3% between two LEDs of said series having a decrease X in defect densities.
    Type: Grant
    Filed: June 19, 2019
    Date of Patent: August 4, 2020
    Assignee: ECOSENSE LIGHTING, INC.
    Inventors: Aurelien J. F. David, Christophe Hurni, Nathan Young
  • Patent number: 10734319
    Abstract: In some implementations, a substrate for coupling to an integrated circuit includes multiple layers. Each of the multiple layers has, in a particular region of the substrate, a repeating pattern of regions corresponding to power and ground. The multiple layers include (i) a top layer having, in the particular region, power contacts and ground contacts for coupling to an integrated circuit and (ii) a bottom layer having, in the particular region, power contacts and ground contacts for coupling to another device. At least one layer of the multiple layers has a repeating pattern of signal traces that extend along and are located between the regions corresponding to ground in the at least one layer.
    Type: Grant
    Filed: October 2, 2018
    Date of Patent: August 4, 2020
    Assignee: Google LLC
    Inventors: Jin Young Kim, Zhonghua Wu
  • Patent number: 10734559
    Abstract: A light-emitting diode (LED) package includes a light-emitting structure, an optical wavelength conversion layer on the light-emitting structure, and an optical filter layer on the optical wavelength conversion layer. The light-emitting structure includes a first-conductivity-type semiconductor layer, an active layer on the first-conductivity-type semiconductor layer, and a second-conductivity-type semiconductor layer on the active layer, and emits first light having a first peak wavelength. The optical wavelength conversion layer absorbs the first light emitted from the light-emitting structure and emits second light having a second peak wavelength different from the first peak wavelength. The optical filter layer reflects the first light emitted from the light-emitting structure and transmits the second light emitted from the optical wavelength conversion layer.
    Type: Grant
    Filed: March 22, 2019
    Date of Patent: August 4, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Ha-nul Yoo, Yong-il Kim, Nam-goo Cha, Wan-tae Lim, Kyung-wook Hwang, Sung-hyun Sim, Hye-seok Noh
  • Patent number: 10727441
    Abstract: A display device includes: a panel unit that includes pixel drive circuits; and a panel terminal unit on an edge portion of the panel unit. The panel terminal unit includes: a board; wiring electrodes disposed on the board and connected to the pixel drive circuits; a mounted component mounted on the board and connected to the wiring electrodes; a protective film that is on the board and covers the wiring electrodes except for a mounting area where the mounted component is mounted on the board; and a resin portion that covers the mounted component and a portion of the protective film and not covers a rest of the protective film.
    Type: Grant
    Filed: June 28, 2019
    Date of Patent: July 28, 2020
    Assignee: JOLED, INC.
    Inventor: Yuki Kishi
  • Patent number: 10727054
    Abstract: A nitride-based semiconductor device includes a patterned substrate having an etched surface that is formed with a plurality of protrusions, an aluminum nitride (AlN)-based film disposed on the etched surface, and a nitride-based semiconductor stacked structure disposed on the aluminum nitride-based film. Each of the protrusions has a side face. The AlN-based film includes a plurality of crystal defects formed on the side face of each protrusion. Each of the crystal defects has a width of smaller than 20 nm and/or the number of the crystal defects that are formed on the side face of each protrusion and that have a width of greater than 10 nm is less than 10. A method for preparing the semiconductor device is also disclosed.
    Type: Grant
    Filed: June 20, 2019
    Date of Patent: July 28, 2020
    Assignee: XIAMEN SAN'AN OPTOELECTRONICS CO., LTD.
    Inventors: Xueliang Zhu, Jianming Liu, Chang-Cheng Chuo, Bing-Yang Chen, Chen-ke Hsu, Chung-Ying Chang