Patents Examined by Nikolay K Yushin
  • Patent number: 10714446
    Abstract: An apparatus is provided which comprises: a substrate; a first active device adjacent to the substrate; a first set of one or more layers to interconnect with the first active device; a second set of one or more layers; a second active and/or passive device coupled to the second set of one or more layers; and a layer adjacent to one of the layers of the first and second sets, wherein the layer is to bond the one of the layers of the first and second sets.
    Type: Grant
    Filed: March 30, 2017
    Date of Patent: July 14, 2020
    Assignee: Intel Corporation
    Inventors: Anup Pancholi, Prashant Majhi, Paul Fischer, Patrick Morrow
  • Patent number: 10707183
    Abstract: A flip chip package includes a substrate having a die attach surface; and a die mounted on the die attach surface with an active surface of the die facing the substrate, wherein the die is interconnected to the substrate via a plurality of copper pillar bumps on the active surface, wherein at least one of the plurality of copper pillar bumps has a bump width that is substantially equal to or smaller than a line width of a trace on the die attach surface of the substrate.
    Type: Grant
    Filed: June 13, 2019
    Date of Patent: July 7, 2020
    Assignee: MEDIATEK INC.
    Inventors: Tzu-Hung Lin, Thomas Matthew Gregorich
  • Patent number: 10707325
    Abstract: A method of forming a complementary metal oxide semiconductor (CMOS) device is provided. The method includes forming a plurality of vertical fins on a substrate, and forming at least two dummy gates across the plurality of vertical fins. The method further includes forming a masking block on one of the at least two dummy gates, and removing the portions of the at least two dummy gates not covered by the masking block, wherein the portion of the one dummy gate covered by the masking block forms a dummy gate plug. The method further includes forming a gate dielectric layer on the exposed surfaces of the plurality of vertical fins and dummy gate plug, and forming a conductive gate layer on the gate dielectric layer, wherein the dummy gate plug physically separates two active gate structures.
    Type: Grant
    Filed: May 29, 2019
    Date of Patent: July 7, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventor: Kangguo Cheng
  • Patent number: 10707179
    Abstract: A semiconductor structure including a MIM capacitor includes a substrate, a MIM capacitor disposed over the substrate, a first insulating layer disposed over the MIM capacitor, an ONON stack disposed over the first insulating layer, a connecting via disposed in the first insulating layer, and a connecting pad disposed in the ONON stack and in contact with the connecting via. The ONON stack covers sidewalls of the connecting pad and a portion of a top surface of the connecting pad.
    Type: Grant
    Filed: June 24, 2019
    Date of Patent: July 7, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Tung-Jiun Wu, Yinlung Lu, Mingni Chang, Ming-Yih Wang
  • Patent number: 10700236
    Abstract: Quantum dot layers and display devices including quantum dot layers are described. In an embodiment the quantum dot layer includes quantum dots with coatings to adjust the spacing between adjacent quantum dots. In an embodiment, the coatings are metal oxide coatings and may create a charge transporting matrix. In an embodiment, the coatings are core-material coatings. The QD layers may be QD-LED compatible.
    Type: Grant
    Filed: September 1, 2017
    Date of Patent: June 30, 2020
    Assignee: Apple Inc.
    Inventors: Jonathan S. Steckel, Hitoshi Yamamoto, Paul S. Drzaic
  • Patent number: 10700098
    Abstract: A display device including a display portion with an extremely high resolution is provided. The display device includes a pixel circuit and a light-emitting element. The pixel circuit includes a first element layer including a first transistor and a second element layer including a second transistor. A channel formation region of the first transistor includes silicon. The first transistor has a function of driving the light-emitting element. The second transistor functions as a switch. A channel formation region of the second transistor includes a metal oxide. The metal oxide functions as a semiconductor. The second element layer is provided over the first element layer.
    Type: Grant
    Filed: July 30, 2019
    Date of Patent: June 30, 2020
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Kei Takahashi, Hiroyuki Miyake
  • Patent number: 10700305
    Abstract: The present disclosure provides a substrate, a display panel and a display device. The substrate includes a body provided with an opening, and guiding protrusions arranged on the body at a position adjacent to the opening.
    Type: Grant
    Filed: May 16, 2019
    Date of Patent: June 30, 2020
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Tao Wang, Ziyu Zhang, Song Zhang
  • Patent number: 10692752
    Abstract: A semiconductor substrate structure and process for fabrication of the semiconductor substrate structure are described. The semiconductor substrate structure includes a silicon carbide (SiC) wafer substrate, an active gallium nitride (GaN) layer and a layer of microcrystalline diamond (MCD) layer disposed between the SiC wafer substrate and the GaN active layer. The MCD) layer is bonded to the SiC wafer substrate and to the GaN active layer.
    Type: Grant
    Filed: June 28, 2019
    Date of Patent: June 23, 2020
    Assignee: ELTA SYSTEMS LTD.
    Inventors: Joseph Kaplun, Bilha Houli Arbiv
  • Patent number: 10692898
    Abstract: The present application discloses a display panel and a display device. The display panel includes an array substrate including a source driver, a gate driver, a plurality of spaced-apart data lines, a plurality of spaced-apart scan lines, and a plurality of spaced-apart connecting line. The source driver is disposed at a first end of the array substrate, the gate driver is disposed at a second end of the array substrate, and the second end is opposite to the first end. The plurality of data lines are respectively connected to the source driver, the plurality of scan lines respectively intersect with the plurality of data lines, the plurality of connecting lines are respectively connected to the gate driver, and each of the connecting lines is respectively connected to one of the scan lines.
    Type: Grant
    Filed: May 30, 2019
    Date of Patent: June 23, 2020
    Assignees: HKC CORPORATION LIMITED, CHONGQING HKC OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventor: Yu-Jen Chen
  • Patent number: 10692973
    Abstract: Techniques are disclosed for forming germanium (Ge)-rich channel transistors including one or more dopant diffusion barrier elements. The introduction of one or more dopant diffusion elements into at least a portion of a given source/drain (S/D) region helps inhibit the undesired diffusion of dopant (e.g., B, P, or As) into the adjacent Ge-rich channel region. In some embodiments, the elements that may be included in a given S/D region to help prevent the undesired dopant diffusion include at least one of tin and relatively high silicon. Further, in some such embodiments, carbon may also be included to help prevent the undesired dopant diffusion. In some embodiments, the one or more dopant diffusion barrier elements may be included in an interfacial layer between a given S/D region and the Ge-rich channel region and/or throughout at least a majority of a given S/D region. Numerous embodiments, configurations, and variations will be apparent.
    Type: Grant
    Filed: April 1, 2017
    Date of Patent: June 23, 2020
    Assignee: INTEL CORPORATION
    Inventors: Glenn A. Glass, Anand S. Murthy, Karthik Jambunathan, Benjamin Chu-Kung, Seung Hoon Sung, Jack T. Kavalieros, Tahir Ghani, Harold W. Kennel
  • Patent number: 10685835
    Abstract: A III-nitride tunnel junction with a modified p-n interface, wherein the modified p-n interface includes a delta-doped layer to reduce tunneling resistance. The delta-doped layer may be doped using donor atoms comprised of Oxygen (O), Germanium (Ge) or Silicon (Si); acceptor atoms comprised of Magnesium (Mg) or Zinc (Zn); or impurities comprised of Iron (Fe) or Carbon (C).
    Type: Grant
    Filed: November 1, 2016
    Date of Patent: June 16, 2020
    Assignees: THE REGENTS OF THE UNIVERSITY OF CALIFORNIA, KING ABDULAZIZ CITY FOR SCIENCE AND TECHNOLOGY (KACST)
    Inventors: Benjamin P. Yonkee, Erin C. Young, John T. Leonard, Tal Margalith, James S. Speck, Steven P. DenBaars, Shuji Nakamura
  • Patent number: 10686050
    Abstract: In a method of manufacturing a semiconductor device, a single crystal oxide layer is formed over a substrate. After the single crystal oxide layer is formed, an isolation structure to define an active region is formed. A gate structure is formed over the single crystal oxide layer in the active region. A source/drain structure is formed.
    Type: Grant
    Filed: May 17, 2019
    Date of Patent: June 16, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventor: Georgios Vellianitis
  • Patent number: 10680111
    Abstract: An object is to provide a semiconductor device having a structure in which parasitic capacitance between wirings can be efficiently reduced. In a bottom gate thin film transistor using an oxide semiconductor layer, an oxide insulating layer used as a channel protection layer is formed above and in contact with part of the oxide semiconductor layer overlapping with a gate electrode layer, and at the same time an oxide insulating layer covering a peripheral portion (including a side surface) of the stacked oxide semiconductor layer is formed. Further, a source electrode layer and a drain electrode layer are formed in a manner such that they do not overlap with the channel protection layer. Thus, a structure in which an insulating layer over the source electrode layer and the drain electrode layer is in contact with the oxide semiconductor layer is provided.
    Type: Grant
    Filed: September 5, 2018
    Date of Patent: June 9, 2020
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Miyuki Hosoba, Junichiro Sakata, Hideaki Kuwabara
  • Patent number: 10680053
    Abstract: A fabrication method for fabricating a thin-film transistor includes: forming a light shielding layer on a substrate; forming a buffer layer covering the light shielding layer, and forming a semiconductor material layer stacked on a surface of the buffer layer away from the substrate; forming a through hole penetrating through the buffer layer and the semiconductor material layer; patterning the semiconductor material layer to form an active layer covering a partial region of the buffer layer; forming a gate insulator layer on a surface of the active layer away from the substrate and a gate stacked on a surface of the gate insulator layer away from the substrate; forming a source and a drain on the surface of the buffer layer away from the substrate; and forming a dielectric layer covering the gate, the source, the drain, and the buffer layer, and being recessed into the through hole to form a groove.
    Type: Grant
    Filed: June 14, 2019
    Date of Patent: June 9, 2020
    Assignees: Hefei Xinsheng Optoelectronics Technology Co., Ltd., BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Yingbin Hu, Liangchen Yan, Ce Zhao, Yuankui Ding, Yang Zhang, Yongchao Huang, Luke Ding, Jun Liu
  • Patent number: 10679932
    Abstract: A semiconductor package is provided, which includes: a substrate having a metal pattern layer; a semiconductor die formed on the substrate; and an underfill filled between the substrate and the semiconductor die. At least an opening is formed in the metal pattern layer to reduce the area of the metal pattern layer on the substrate, thereby reducing the contact area between the underfill and the metal pattern layer, hence eliminating the underfill delamination.
    Type: Grant
    Filed: April 27, 2017
    Date of Patent: June 9, 2020
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Chang-Fu Lin, Ho-Yi Tsai, Chin-Tsai Yao
  • Patent number: 10673020
    Abstract: A display panel includes a base substrate including a display area surrounding a hole area, a circuit layer including insulation layers, where an opening is defined through each insulation layer to overlap the hole area, an element layer including an organic light emitting element connected to a transistor, an encapsulation layer disposed on the element layer and including first and second encapsulation inorganic layers and an organic layer, a cover inorganic layer overlapping the hole area and disposed between the first encapsulation inorganic layer and the insulation layers. A module hole is defined through the display panel, and a first groove is defined by portions of the cover inorganic layer and the first and second encapsulation inorganic layers which cover inner surface of the opening and the recess part. The cover inorganic layer contacts the inner surfaces of the opening and the recess part.
    Type: Grant
    Filed: July 12, 2019
    Date of Patent: June 2, 2020
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventor: Namjin Kim
  • Patent number: 10672624
    Abstract: A method of making a semiconductor device may include providing a carrier comprising a semiconductor die mounting site. A build-up interconnect structure may be formed over the carrier. A first portion of a conductive interconnect may be formed over the build-up interconnect structure in a periphery of the semiconductor die mounting site. An etch stop layer and a second portion of the conductive interconnect may be formed over the first portion of the conductive interconnect. A semiconductor die may be mounted to the build-up interconnect at the semiconductor die mounting site. The conductive interconnect and the semiconductor die may be encapsulated with a mold compound. A first end of the conductive interconnect on the second portion of the conductive interconnect may be exposed. The carrier may be removed to expose the build-up interconnect structure. The first portion of the conductive interconnect may be etched to expose the etch stop layer.
    Type: Grant
    Filed: June 19, 2018
    Date of Patent: June 2, 2020
    Assignee: Deca Technologies Inc.
    Inventors: Christopher M. Scanlan, William Boyd Rogers, Craig Bishop
  • Patent number: 10672798
    Abstract: A method of manufacturing an active array substrate, comprising: providing a substrate; forming gate electrodes on the substrate; forming a gate insulating layer, a semiconductor layer and an Ohmic contact layer on the transparent substrate and the gate electrodes in order; forming source electrodes and drain electrodes on the Ohmic contact layer; forming a protection layer on the source electrodes and the drain electrodes; and forming a pixel electrode layer on the protection layer, wherein the pixel electrode layer is electrically connected to the drain electrode. The gate insulating layer comprises nanometer porous silicon and nanometer particles, and a dielectric constant of the nanometer particle is greater than a dielectric constant of the nanometer porous silicon.
    Type: Grant
    Filed: October 16, 2017
    Date of Patent: June 2, 2020
    Assignees: HKC CORPORATION LIMITED, CHONGQING HKC OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventor: En-Tsung Cho
  • Patent number: 10672948
    Abstract: Aspects of the disclosure provide for mechanisms for fabricating light extraction structures for semiconductor devices (e.g., light-emitting devices). In accordance with some embodiments, a semiconductor device is provided. The semiconductor device may include: a first semiconductor layer including an epitaxial layer of a semiconductor material; a second semiconductor layer comprising an active layer; and a light-reflection layer configured to cause at least a portion of light produced by the active layer to emerge from the semiconductor device via a surface of the second semiconductor layer, wherein the light-reflection layer is positioned between the first semiconductor layer and the second semiconductor layer. In some embodiments, the semiconductor material includes gallium nitride. In some embodiments, the light-reflection layer includes a layer of gallium.
    Type: Grant
    Filed: December 15, 2017
    Date of Patent: June 2, 2020
    Assignee: Saphlux, Inc.
    Inventors: Joo Won Choi, Chen Chen
  • Patent number: 10672906
    Abstract: A transistor device disposed on a substrate and including a semiconductor layer, a first gate, a second gate, and two source drain electrodes is provided. The semiconductor layer is disposed on the substrate and has a channel region, two lightly-doped regions, and two source drain regions. Each of the two lightly-doped regions has a first boundary adjoined to the channel region and a second boundary adjoined to one of the two source drain regions. The first gate is extended over the channel region of the semiconductor layer, wherein an edge of the first gate is aligned with the first boundary. The second gate is stacked on the first gate and is in contact with the first gate, wherein in a thickness direction, the second gate is overlapped with the two lightly-doped regions. The two source drain electrodes are respectively in contact with the two source drain regions.
    Type: Grant
    Filed: July 4, 2019
    Date of Patent: June 2, 2020
    Assignee: Au Optronics Corporation
    Inventors: Ming-Yan Chen, Ming-Hsien Lee, Che-Chia Chang