Abstract: An active matrix substrate has pixel regions, and includes a substrate, pixel TFTs disposed to respectively correspond to the pixel regions, and pixel electrodes electrically connected to the pixel TFTs. The pixel TFTs are each a top gate structure TFT that has an oxide semiconductor layer, a gate insulating layer on the oxide semiconductor layer, and a gate electrode opposing the oxide semiconductor layer with the gate insulating layer therebetween. The gate insulating layer is formed of silicon oxide and includes a lower layer contacting the oxide semiconductor layer, and an upper layer on the lower layer. The lower layer H/N ratio of hydrogen atoms to nitrogen atoms in the lower layer is 1.5 to 5.0. The upper layer H/N ratio of hydrogen atoms to nitrogen atoms in the upper layer is 0.9 to 2.0. The lower layer H/N ratio is larger than the upper layer H/N ratio.

Abstract: The present disclosure provides a display device comprising: a first thin film transistor including a first semiconductor pattern disposed on a substrate and comprising poly-silicon, and a first gate electrode; a middle layer on the first gate electrode; a second thin film transistor including a second semiconductor pattern disposed on the middle layer and comprising an oxide semiconductor, and a second gate electrode; and a storage capacitor including first to fourth storage electrodes overlapping with each other.

Abstract: A semiconductor device having favorable and stable electrical characteristics is provided. The semiconductor device includes a first and a second transistor over an insulating surface. The first and the second transistors each include a first insulating layer, a semiconductor layer over the first insulating layer, a second insulating layer over the semiconductor layer, and a first conductive layer overlapping with the semiconductor layer with the second insulating layer interposed therebetween. The first insulating layer includes a convex first region that overlaps with the semiconductor layer and a second region that does not and is thinner than the first region. The first conductive layer includes a part over the second region where a lower surface of the first conductive layer is positioned below a lower surface of the semiconductor layer. The second transistor further includes a third conductive layer overlapping with the semiconductor layer with the first insulating layer interposed therebetween.

Abstract: A semiconductor package includes a first semiconductor chip including a first body portion, a first bonding layer including a first bonding insulating layer, a first redistribution portion including first redistribution layers, a first wiring insulating layer disposed between the first redistribution layers, and a second bonding layer including a second bonding insulating layer, a second redistribution portion including second redistribution layers, a second wiring insulating layer disposed between the second redistribution layers, and a second semiconductor chip disposed on the second redistribution portion. A lower surface of the first bonding insulating layer is bonded to an upper surface of the second bonding insulating layer, an upper surface of the first bonding insulating layer contacts the first body portion, a lower surface of the second bonding insulating layer contacts the second wiring insulating layer, and the first redistribution portion width is greater than the first semiconductor chip width.

Abstract: This disclosure discloses an array substrate, and a production method, a display panel, and a display apparatus thereof. Particularly, this disclosure proposes a method of producing an array substrate, having the following steps: providing a substrate having a drive transistor region and a switch transistor region thereon; forming an preset layer for active layer on a side of the substrate; patterning the preset layer for active layer to form a drive active layer and a switch active layer, wherein an orthographic projection of the drive active layer on the substrate is located in the drive transistor region, an orthographic projection of the switch active layer on the substrate is located in the switch transistor region, and a carrier concentration in the drive active layer is less than a carrier concentration in the switch active layer.

Abstract: A workpiece unit that includes a workpiece, a tape stuck to the workpiece; and an annular frame to which an outer circumferential edge of the tape is stuck and which has an opening defined centrally therein. The workpiece is disposed in the opening in the annular frame and supported on the annular frame by the tape, and at least one of the tape and the annular frame has an irreversible discoloring section that discolors in response to an external stimulus. Such a configuration makes it possible to determine whether or not a process involving an external stimulus has been carried out on the workpiece unit, based on the appearance of the workpiece unit (i.e., based on whether the irreversible discoloring section has been discolored or not).

Abstract: A semiconductor device with high reliability is provided. The semiconductor device includes a first insulator, a second insulator, and a transistor; the transistor includes an oxide in a channel formation region; the oxide is surrounded by the first insulator; and the first insulator is surrounded by the second insulator. The first insulator includes a region with a lower hydrogen concentration than the second insulator. Alternatively, the first insulator includes a region with a lower hydrogen concentration than the second insulator and with a lower nitrogen concentration than the second insulator.

Abstract: A semiconductor device in which variations in characteristics, deterioration of elements, and abnormality in shape are inhibited is provided. The semiconductor device includes a first region including a plurality of elements and a second region including a plurality of dummy elements. The second region is provided in an outer edge of the first region, and the element and the dummy element each include an oxide semiconductor. The element and the dummy element have the same structure, and a structure body included in the element and a structure body included in the dummy element are formed with the same material and provided in the same layer. The oxide semiconductor includes In, an element M (M is Al, Ga, Y, or Sn), and Zn.

Abstract: According to one embodiment, a display device comprises a first substrate, a second substrate opposed to the first substrate and including a first organic film, a first convex portion extending in a first direction, a second convex portion extending in a second direction intersecting the first direction, and a third convex portion aligned with the first convex portion in the second direction and extending in the first direction, and a sealing member located in a second area around a first area in which an image is displayed, wherein the first convex portion, the second convex portion and the third convex portion are located between the first organic film and the sealing member.

Abstract: A light-emitting diode is disclosed, which includes: a substrate; a light-emitting diode chip disposed on the substrate; and a quantum dot film disposed on the light-emitting diode chip, wherein the quantum dot film includes a plurality of quantum dots and a matrix material, and a plurality of particles are dispersed in the matrix material, wherein the plurality of particles are conductive particles, semiconductor particles, or a combination thereof.

Abstract: A vaporizer includes a tank in which liquid material is heated to generate gas, a cabinet which houses the tank, and a conduit which supplies the gas to the outside of the cabinet. The vaporizer also includes a flow rate measuring means which measures a flow rate of the gas flowing through said conduit, and a heater plate which heats the conduit. The cabinet comprises a detachable panel that is a panel which can be removed. A first support member is fixed directly or indirectly to said cabinet at a position other than said detachable panel, the flow rate measuring means is supported by said first support member, and the heater plate is supported between said flow rate measuring means and said detachable panel by said first support member.

Abstract: A liquid crystal display device with a high aperture ratio is provided. A liquid crystal display device with low power consumption is provided. A display device includes a transistor and a capacitor. The transistor includes a first insulating layer, a first semiconductor layer in contact with the first insulating layer, a second insulating layer in contact with the first semiconductor layer, and a first conductive layer electrically connected to the first semiconductor layer via an opening portion provided in the second insulating layer. The capacitor includes a second conductive layer in contact with the first insulating layer, the second insulating layer in contact with the second conductive layer, and the first conductive layer in contact with the second insulating layer. The second conductive layer includes a composition similar to that of the first semiconductor layer. The first conductive layer and the second conductive layer are configured to transmit visible light.

Abstract: A method of manufacturing a display panel and a display panel are provided. A groove is formed on a buffer layer through performing exposure and etching processes, so as to divide the buffer layer into independent units. A gate insulating layer, a dielectric layer, and a passivation layer are converted from continuous layers to independent layers on the buffer layer. Therefore, heterogeneous interface stress accumulated in the independent unit is reduced, it prevents the deformation of the glass substrate, protects the glass substrate, reduces fragmentation phenomenon, and improves process reliability and yield.

Abstract: A method includes placing an electronic die and a photonic die over a carrier, with a back surface of the electronic die and a front surface of the photonic die facing the carrier. The method further includes encapsulating the electronic die and the photonic die in an encapsulant, planarizing the encapsulant until an electrical connector of the electronic die and a conductive feature of the photonic die are revealed, and forming redistribution lines over the encapsulant. The redistribution lines electrically connect the electronic die to the photonic die. An optical coupler is attached to the photonic die. An optical fiber attached to the optical coupler is configured to optically couple to the photonic die.

Abstract: A test element group (TEG) test key of an array substrate and a display panel thereof are provided. The TEG test key of the array substrate includes a glass substrate, a multi-buffer layer, an active layer, a gate insulating layer, a gate electrode layer, an interlayer insulating layer, a source and drain electrode layer, and an organic planarization layer stacked in sequence. The TEG test key of the array substrate is defined with two test zones and a connecting zone, and each test zone is provided with a groove exposing the gate electrode layer. The gate electrode layer in the test zones is electrically connected to the source and drain electrode layer in the connecting zone.

Abstract: The present application provides an array substrate and a display device. The array substrate includes a first conductive layer, a second conductive layer, and an insulating layer. The first conductive layer includes at least two first conductive members disposed side by side in the bonding area. The second conductive layer includes at least two second conductive members; each of the second conductive members is provided corresponding to and electrically connected to each of the first conductive members, and at least two of the second conductive members and at least two of the first conductive members are electrically connected through a same via-hole on the insulating layer.

Abstract: A vertical memory device may include a channel connecting pattern on a substrate, gate electrodes spaced apart from each other in a first direction on the channel connecting pattern, and a channel extending in the first direction through the gate electrodes and the channel connecting pattern. Each of the electrodes may extend in a second direction substantially parallel to an upper surface of the substrate, and the first direction may be substantially perpendicular to the upper surface of the substrate. An end portion of the channel connecting pattern in a third direction substantially parallel to the upper surface of the substrate and substantially perpendicular to the second direction may have an upper surface higher than an upper surface of other portions of the channel connecting pattern except for a portion thereof adjacent the channel.

Abstract: The present disclosure describes epitaxial oxide integrated circuits. In some embodiments, an integrated circuit comprises: a field effect transistor (FET), comprising: a substrate comprising a first oxide material; an epitaxial buried ground plane on the substrate and comprising a second oxide material; an epitaxial buried oxide layer on the epitaxial buried ground plane and comprising a third oxide material; an epitaxial semiconductor layer on the epitaxial buried oxide layer and comprising a fourth oxide material with a first bandgap; a gate layer on the epitaxial semiconductor layer and comprising a fifth oxide material with a second bandgap; electrical contacts; and a waveguide coupled to the field effect transistor. The waveguide can comprise: the epitaxial buried ground plane; the epitaxial buried oxide layer; and a signal conductor, wherein the epitaxial buried oxide layer is between the signal conductor and the epitaxial buried ground plane.

Abstract: The disclosure provides a display panel, a manufacturing method thereof, and a display device. The display panel includes a substrate layer, a gate layer, an insulating layer, and an active layer. The gate layer is disposed on the substrate layer and includes a first gate layer and a second gate layer. The second gate layer is disposed on a surface of the first gate layer. The insulating layer covers the gate layer and the substrate layer. The active layer is disposed on a surface of the insulating layer away from the gate layer. The active layer includes a first layer section and a second layer section connected to the first layer section, and a surface of the second layer section is above a surface of the first section layer.

Abstract: A display panel and method of manufacturing the same are provided. The method of manufacturing the display panel includes the steps of providing a substrate, forming a gate on the substrate, forming a gate insulating layer on the gate and the substrate, forming a polysilicon layer on the gate insulating layer, performing a first gray-scale mask process on the polysilicon layer to form a source region, a drain region and an active region located between the source region and the drain region by the polysilicon layer, forming an interlayer dielectric layer on the gate insulating layer and the polysilicon layer, forming a first electrode layer on the interlayer dielectric layer, performing a second gray-scale mask process on the first electrode layer and the interlayer dielectric layer.