Patents Examined by Nikolay K Yushin
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Patent number: 11521987Abstract: A vertical memory device may include a channel connecting pattern on a substrate, gate electrodes spaced apart from each other in a first direction on the channel connecting pattern, and a channel extending in the first direction through the gate electrodes and the channel connecting pattern. Each of the electrodes may extend in a second direction substantially parallel to an upper surface of the substrate, and the first direction may be substantially perpendicular to the upper surface of the substrate. An end portion of the channel connecting pattern in a third direction substantially parallel to the upper surface of the substrate and substantially perpendicular to the second direction may have an upper surface higher than an upper surface of other portions of the channel connecting pattern except for a portion thereof adjacent the channel.Type: GrantFiled: March 9, 2021Date of Patent: December 6, 2022Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Ji-Hoon Choi, Sung-Gil Kim, Jung-Hwan Kim, Chan-Hyoung Kim, Woo-Sung Lee
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Patent number: 11522087Abstract: The present disclosure describes epitaxial oxide integrated circuits. In some embodiments, an integrated circuit comprises: a field effect transistor (FET), comprising: a substrate comprising a first oxide material; an epitaxial buried ground plane on the substrate and comprising a second oxide material; an epitaxial buried oxide layer on the epitaxial buried ground plane and comprising a third oxide material; an epitaxial semiconductor layer on the epitaxial buried oxide layer and comprising a fourth oxide material with a first bandgap; a gate layer on the epitaxial semiconductor layer and comprising a fifth oxide material with a second bandgap; electrical contacts; and a waveguide coupled to the field effect transistor. The waveguide can comprise: the epitaxial buried ground plane; the epitaxial buried oxide layer; and a signal conductor, wherein the epitaxial buried oxide layer is between the signal conductor and the epitaxial buried ground plane.Type: GrantFiled: April 8, 2022Date of Patent: December 6, 2022Assignee: Silanna UV Technologies Pte LtdInventor: Petar Atanackovic
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Patent number: 11522088Abstract: The disclosure provides a display panel, a manufacturing method thereof, and a display device. The display panel includes a substrate layer, a gate layer, an insulating layer, and an active layer. The gate layer is disposed on the substrate layer and includes a first gate layer and a second gate layer. The second gate layer is disposed on a surface of the first gate layer. The insulating layer covers the gate layer and the substrate layer. The active layer is disposed on a surface of the insulating layer away from the gate layer. The active layer includes a first layer section and a second layer section connected to the first layer section, and a surface of the second layer section is above a surface of the first section layer.Type: GrantFiled: November 27, 2019Date of Patent: December 6, 2022Assignee: Shenzhen China Star Optoelectronics Semiconductor Display Technology Co., Ltd.Inventor: Huafei Xie
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Patent number: 11521993Abstract: A display panel and method of manufacturing the same are provided. The method of manufacturing the display panel includes the steps of providing a substrate, forming a gate on the substrate, forming a gate insulating layer on the gate and the substrate, forming a polysilicon layer on the gate insulating layer, performing a first gray-scale mask process on the polysilicon layer to form a source region, a drain region and an active region located between the source region and the drain region by the polysilicon layer, forming an interlayer dielectric layer on the gate insulating layer and the polysilicon layer, forming a first electrode layer on the interlayer dielectric layer, performing a second gray-scale mask process on the first electrode layer and the interlayer dielectric layer.Type: GrantFiled: September 25, 2018Date of Patent: December 6, 2022Assignee: Wuhan China Star Optoelectronics Technology Co., Ltd.Inventors: Chao Wang, Guanghui Liu, Yuan Yan
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Patent number: 11515429Abstract: A thin film transistor includes at least a gate electrode, a gate insulating film, an oxide semiconductor layer, source/drain electrodes, and at least one layer of a passivation film on a substrate. Metal elements constituting the oxide semiconductor layer include In, Ga, Zn, and Sn. Respective ratios of the metal elements to a total (In+Ga+Zn+Sn) of the metal elements in the oxide semiconductor layer satisfy: In: 30 atom % or more and 45 atom % or less, Ga: 5 atom % or more and less than 20 atom %, Zn: 30 atom % or more and 60 atom % or less, and Sn: 4.0 atom % or more and less than 9.0 atom %.Type: GrantFiled: April 23, 2019Date of Patent: November 29, 2022Assignee: Kobe Steel, Ltd.Inventors: Mototaka Ochi, Hiroshi Goto
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Patent number: 11508851Abstract: A semiconductor device includes: a substrate including an active region and a device isolation region; a flat plate structure formed on the substrate; an oxide semiconductor layer covering a top surface of the flat plate structure and continuously arranged on a top surface of the substrate in the active region and the device isolation region; a gate structure arranged on the oxide semiconductor layer and including a gate dielectric layer and a gate electrode; and a source/drain region arranged on both sides of the gate structure and formed in the oxide semiconductor layer, in which, when viewed from a side cross-section, an extending direction of the flat plate structure and an extending direction of the gate structure cross each other.Type: GrantFiled: August 27, 2020Date of Patent: November 22, 2022Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Minhee Cho, Hyunmog Park, Minwoo Song, Woobin Song, Hyunsil Oh, Minsu Lee
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Patent number: 11502065Abstract: A method of manufacturing a display apparatus including steps of forming a plurality of light emitting diode chips spaced apart from one another at a predetermined interval on a first manufacturing substrate and transferring the light emitting diode chips to a second manufacturing substrate by laser irradiation, in which the light emitting diode chips include a light emitting structure including a first-type semiconductor layer and a second-type semiconductor layer, a first-type electrode disposed on the first-type semiconductor layer, and a second-type electrode disposed on the second-type semiconductor layer.Type: GrantFiled: September 2, 2020Date of Patent: November 15, 2022Assignee: Seoul Semiconductor Co., Ltd.Inventor: Motonobu Takeya
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Patent number: 11502115Abstract: An active matrix substrate includes a substrate, a first gate bus line, a second gate bus line, a third gate bus line, a first source bus line, a second source bus line, a first pixel region, a second pixel region, and a first source contact portion. When viewed from a normal direction of the substrate, a first opening portion is located between the second gate bus line and the third gate bus line, and a first distance D1 in a column direction between the second gate bus line and the first opening portion and a second distance D2 in the column direction between the third gate bus line and the first opening portion are both ? or more of a second interval Dy2 in the column direction between the second gate bus line and the third gate bus line.Type: GrantFiled: April 14, 2021Date of Patent: November 15, 2022Assignee: SHARP KABUSHIKI KAISHAInventors: Masahiko Suzuki, Tetsuo Kikuchi, Setsuji Nishimiya, Kengo Hara, Hitoshi Takahata, Tohru Daitoh
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Patent number: 11488990Abstract: An active matrix substrate includes a thin film transistor that includes a gate electrode, a first inorganic insulating film that covers the gate electrode, a second inorganic insulating film that is disposed on the first inorganic insulating film and that has an opening overlapping the gate electrode, a source electrode and a drain electrode disposed on the second inorganic insulating film, and a semiconductor layer that overlaps the gate electrode in an opening of the first inorganic insulating film and that covers the source electrode and the drain electrode. Regarding a surface of the first inorganic insulating film in a first region overlapping the opening of the first inorganic insulating film and a surface in a second region other than the first region, the surfaces being arranged nearer to the second inorganic insulating film, the surface in the first region is lower than the surface in the second region.Type: GrantFiled: April 28, 2020Date of Patent: November 1, 2022Assignee: SHARP KABUSHIKI KAISHAInventor: Katsunori Misaki
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Patent number: 11482625Abstract: A novel oxide semiconductor, a novel oxynitride semiconductor, a transistor including them, or a novel sputtering target is provided. A composite target includes a first region and a second region. The first region includes an insulating material and the second region includes a conductive material. The first region and the second region each include a microcrystal whose diameter is greater than or equal to 0.5 nm and less than or equal to 3 nm or a value in the neighborhood thereof. A semiconductor film is formed using the composite target.Type: GrantFiled: September 17, 2019Date of Patent: October 25, 2022Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventor: Shunpei Yamazaki
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Patent number: 11476314Abstract: A display device according to the disclosure includes a substrate, a first transistor provided on the substrate, and a second transistor provided on the substrate, not overlapping the first transistor. The first transistor includes a polycrystalline silicon layer provided on the substrate, a first insulating film provided on the polycrystalline silicon layer, a first gate electrode provided on the first insulating film, and a second insulating film provided on the first gate electrode. The second transistor includes an oxide semiconductor layer provided on the first insulating film, a third insulating film provided on the oxide semiconductor layer, and a second gate electrode provided on the third insulating film. The first and third insulating films are SiOx films. The second insulating film is an SiNx film including hydrogen, and is provided overlapping the polycrystalline silicon layer, and is provided not overlapping the oxide semiconductor layer.Type: GrantFiled: March 29, 2018Date of Patent: October 18, 2022Assignee: SHARP KABUSHIKI KAISHAInventors: Masatomo Honjo, Hiroshi Matsukizono, Takuya Matsuo
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Patent number: 11462412Abstract: The present disclosure relates to an etching method including: a first step of forming an etching assistance layer on a surface of at least one of a plurality of silicon-containing regions by plasma of a processing gas generated in a processing container; and a second step of imparting energy to the etching assistance layer. The energy is equal to or greater than energy at which the etching assistance layer is removed, and smaller than energy at which a region located immediately below the etching assistance layer is sputtered, and a sequence including the first step and the second step is executed repeatedly.Type: GrantFiled: January 3, 2020Date of Patent: October 4, 2022Assignee: TOKYO ELECTRON LIMITEDInventor: Akihiro Tsuji
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Patent number: 11456187Abstract: A semiconductor device for high power application in which a novel semiconductor material having high mass productivity is provided. An oxide semiconductor film is formed, and then, first heat treatment is performed on the exposed oxide semiconductor film in order to reduce impurities such as moisture or hydrogen in the oxide semiconductor film. Next, in order to further reduce impurities such as moisture or hydrogen in the oxide semiconductor film, oxygen is added to the oxide semiconductor film by an ion implantation method, an ion doping method, or the like, and after that, second heat treatment is performed on the exposed oxide semiconductor film.Type: GrantFiled: July 2, 2020Date of Patent: September 27, 2022Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Shunpei Yamazaki, Junichiro Sakata, Hiroki Ohara
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Patent number: 11456365Abstract: An example memory device includes a channel positioned between and electrically connecting a first diffusion region and a second diffusion region, and a tunnel dielectric layer, a multi-layer charge trapping layer, and a blocking dielectric layer disposed between the gate structure and the channel. The multi-layer charge trapping layer includes a first dielectric layer disposed abutting a second dielectric layer and an anti-tunneling layer disposed between the first and second dielectric layers. The anti-tunneling layer includes an oxide layer. The first dielectric layer includes oxygen-rich nitride and the second dielectric layer includes oxygen-lean nitride.Type: GrantFiled: January 25, 2021Date of Patent: September 27, 2022Assignee: LONGITUDE FLASH MEMORY SOLUTIONS LTD.Inventors: Igor Polishchuk, Sagy Charel Levy, Krishnaswamy Ramkumar
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Patent number: 11444103Abstract: An array substrate and a method of manufacturing thereof are provided. The array substrate includes a substrate, a buffer layer, a plurality of thin film transistors, an organic layer, and a first electrode. By defining a via hole between two adjacent thin film transistors in the bending region, the via hole penetrates through the passivation layer, the gate insulating layer, and the first metal trace, which can effectively reduce stress between the passivation layer and the gate insulating layer.Type: GrantFiled: November 8, 2019Date of Patent: September 13, 2022Assignee: Wuhan China Star Optoelectronics Technology Co., Ltd.Inventor: Bingkun Yin
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Patent number: 11437520Abstract: The transistor includes a first insulating film, an oxide semiconductor layer, a gate insulating film, an upper gate electrode, and a second insulating film being sequentially layered on a substrate, and the transistor includes a light blocking layer layered on the second insulating film and formed of metal. The light blocking layer is electrically connected to the upper gate electrode by interposing a gate contact hole provided in the second insulating film. The oxide semiconductor layer is configured such that a region overlapping with the upper gate electrode entirely overlaps with the light blocking layer.Type: GrantFiled: March 30, 2018Date of Patent: September 6, 2022Assignee: SHARP KABUSHIKI KAISHAInventors: Tadayoshi Miyamoto, Yoshinobu Nakamura
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Patent number: 11430897Abstract: A semiconductor device with favorable electrical characteristics is provided. A semiconductor device having stable electrical characteristics is provided. A highly reliable semiconductor device is provided. The semiconductor device includes a semiconductor layer, a first insulating layer, a second insulating layer, and a conductive layer. The first insulating layer is in contact with part of the top surface of the semiconductor layer, the conductive layer is positioned over the first insulating layer, and the second insulating layer is positioned over the semiconductor layer. The semiconductor layer contains a metal oxide and includes a first region overlapping with the conductive layer and a second region not overlapping with the conductive layer. The second region is in contact with the second insulating layer. The second insulating layer contains oxygen and a first element. The first element is one or more of phosphorus, boron, magnesium, aluminum, and silicon.Type: GrantFiled: March 12, 2019Date of Patent: August 30, 2022Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Junichi Koezuka, Yasutaka Nakazawa
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Patent number: 11430655Abstract: Techniques for deposition of high-density dielectric films for patterning applications are described. More particularly, a method of processing a substrate is provided. The method includes flowing a precursor-containing gas mixture into a processing volume of a processing chamber having a substrate positioned on an electrostatic chuck. The substrate is maintained at a pressure between about 0.1 mTorr and about 10 Torr. A plasma is generated at the substrate level by applying a first RF bias to the electrostatic chuck to deposit a dielectric film on the substrate. The dielectric film has a refractive index in a range of about 1.5 to about 3.Type: GrantFiled: October 13, 2020Date of Patent: August 30, 2022Assignee: Applied Materials, Inc.Inventors: Eswaranand Venkatasubramanian, Samuel E. Gottheim, Pramit Manna, Abhijit Basu Mallick
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Patent number: 11430830Abstract: A white LED and a method of repairing a light emitting device including, the method including colored light emitting diodes (LEDs) configured to emit different colors of light and arranged in pixels on a backplane of the device, the method including: determining whether each pixel is a functional pixel or a defective pixel; and repairing the defective pixels by transferring white LEDs to the backplane in each defective pixel.Type: GrantFiled: April 1, 2020Date of Patent: August 30, 2022Assignee: NANOSYS, INC.Inventors: Fariba Danesh, Zhen Chen
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Patent number: 11430844Abstract: An array substrate, a manufacturing method thereof and an organic light emitting diode display device are provided. The manufacturing method of the array substrate includes forming a first thin film transistor including a first semiconductor pattern, including forming a first electrode pattern including a first source electrode and a first drain electrode and a second electrode pattern including a first auxiliary source electrode and a first auxiliary drain electrode respectively through two patterning processes; forming a second thin film transistor including forming a second source electrode and a second drain electrode through one patterning process. The second electrode pattern, the second source electrode and the second drain electrode are formed in the same patterning process, the first electrode pattern is connected with the first semiconductor pattern.Type: GrantFiled: November 15, 2018Date of Patent: August 30, 2022Assignee: BOE TECHNOLOGY GROUP CO., LTD.Inventor: Wei Yang