Abstract: A light-emitting device includes first and second lead frames spaced apart from each other, the first and second lead frames each including a top surface, an opposing bottom surface, and sidewalls arranged between the top surface and the bottom surface thereof, in which at least one of the first and second lead frames include three inset sidewalls that at least partially define a fixing space, the fixing space undercutting at least one of the first lead frame and second lead frame, a light-emitting diode chip disposed on the top surface of the first or second lead frame, and the top surfaces of the first and second lead frames are substantially flat.

Abstract: The invention relates to a light emitting device, a manufacturing method thereof and a display device. The light emitting device comprises: a substrate, and a first electrode layer, a second electrode layer and a light emitting layer arranged above the substrate, the light emitting layer being disposed between the first electrode layer and the second electrode layer, the light emitting layer comprises a hole transport layer having a first thickness which is capable of avoiding performance degradation of the light emitting device.

Abstract: A nonvolatile resistive switching memory, comprising an inert metal electrode, a resistive switching functional layer, and an easily oxidizable metal electrode, and characterized in that: a graphene barrier layer is inserted between the inert metal electrode and the resistive switching functional layer, which is capable of preventing the easily oxidizable metal ions from migrating into the inert metal electrode through the resistive switching functional layer under the action of electric field during the programming of the device.

Abstract: A semiconductor device and methods for manufacturing the same are disclosed. The semiconductor device includes a polymer substrate and an interfacial layer over the polymer substrate. A buried oxide layer resides over the interfacial layer, and a device layer with at least a portion of a radio frequency power switch that has a root mean square breakdown voltage in a range from 80 V to 200 V resides over the buried oxide layer. The polymer substrate is molded over the interfacial adhesion layer and has a thermal conductivity greater than 2 watts per meter Kelvin (W/mK) and an electrical resistivity greater than 1012 Ohm-cm. Methods of manufacture for the semiconductor device include removing a wafer handle to expose a first surface of the buried oxide layer, disposing the interfacial adhesion layer onto the first surface of the buried oxide layer, and molding the polymer substrate onto the interfacial adhesion layer.

Abstract: A semiconductor structure includes stack structures. Each of the stack structures comprises a first conductive material, a chalcogenide material over the first conductive material, a second conductive material over the chalcogenide material, and a first dielectric material between the chalcogenide material and the first conductive material and between the chalcogenide material and the second conductive material. The semiconductor structure further comprises a second dielectric material on at least sidewalls of the chalcogenide material. The chalcogenide material may be substantially encapsulated by one or more dielectric materials. Related semiconductor structures and related methods are disclosed.

Abstract: A high-voltage field effect transistor a heterojunction is disposed between the first and second semiconductor material. A first composite passivation layer includes a first insulation layer and a first passivation layer, and a second composite passivation layer includes a second insulation layer and a second passivation layer. The first insulation layer is disposed between the first passivation layer and the second passivation layer, and the second passivation layer is disposed between the first insulation layer and the second insulation layer. A gate dielectric disposed between the second semiconductor material and the first passivation layer. A gate electrode is disposed above the gate dielectric. A first gate field plate is disposed between the first passivation layer and the second passivation layer. A source electrode and a drain electrode are coupled to the second semiconductor material.

Abstract: This application provides a high power semiconductor device, which is characterized by forming two diodes connected in parallel and a schottky contact on a channel layer to lower the turn-on voltage and turn-on resistance of the high power semiconductor device at the same time and to enhance the breakdown voltage.

Abstract: A system for counting steps comprising a 3-D accelerometer is disclosed. The system also includes a pre-processor module coupled to the 3-D accelerometer and a dominant component computation unit coupled to the pre-processor module. The dominant component computation unit is configured to identify a dominant component in an output of the 3-D accelerometer. The system further includes a step counter for counting a number of steps using the output of the dominant component computation unit. The step counter includes a Fast Fourier Transform (FFT) module and a direct current (DC) remover module to remove a static component from the output of the FFT module. The step counter also includes a derivative filter and a zero crossing detector.

Abstract: Integrated circuits and methods of producing the same are provided. In an exemplary embodiment, an integrated circuit includes a substrate with a handle layer, a buried insulator layer overlying the handle layer, and an active layer overlying the buried insulator layer. The handle layer and the active layer include monocrystalline silicon. A transistor overlies the buried insulator layer, and a solar cell is within the handle layer such that the buried insulator layer is between the solar cell and the transistor. The solar cell includes a solar cell outer layer in electrical communication with a solar cell outer layer contact, and a solar cell inner layer in electrical communication with a solar cell inner layer contact. The solar cell inner and outer layers are monocrystalline silicon.

Abstract: A sensor system responsive to acoustic or seismic signals. One system includes a frame and a piezo-electric sensor element. The sensor element, responsive to a wavefield of seismic or acoustic energy, is positioned about the frame. Coupling between the sensor element and the frame is so limited as to render direct coupling of the sensor element with the wavefield the predominant means for stimulating the sensor element with seismic energy. Another system includes a frame and a cable element, responsive to a seismic or acoustic wavefield, extending about the frame. Coupling between the cable element and frame is so limited as to render direct coupling of the sensor element with the wavefield the predominant means for stimulating the sensor element with acoustic or seismic energy. The element may be coaxial cable or have piezo-electric properties to generate a charge differential measurable as a voltage between conductors.

Abstract: A thin-film transistor is provided. The thin film transistor includes a substrate; an active layer configured as a channel of the thin-film transistor, wherein the active layer is a mixture of oxide semiconductor and graphene; and a source and a drain.

Abstract: A flexible display device includes a flexible substrate, an inorganic barrier layer, a metal layer, an organic buffer layer, and an insulating layer. The inorganic barrier layer is located on the flexible substrate. The metal layer is located on the inorganic barrier layer and in contact with the inorganic barrier layer. The organic buffer layer covers the inorganic barrier layer and the metal layer, and has at least one conductive via connected to the metal layer. The insulating layer is located on the organic buffer layer.

Abstract: A machine for testing the parts and functions of a mobile phone includes a supporting mechanism, a platform, a receiving portion, and a detecting mechanism. The supporting mechanism is mounted in a box. The platform is slidably mounted on the supporting mechanism. The receiving portion is used to receive the mobile phone. The receiving portion is rotatably mounted on the platform. Devices within the machine are operated to test the mobile phone. A mobile phone testing system used in the testing machine is also described.

Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a bottom layer over a substrate and forming a middle layer over the bottom layer. The middle layer includes a carbon backbone and a first side chain bonded to the carbon backbone, and the first side chain has a hydrophilic group. The method includes forming a top layer over the middle layer and patterning the top layer to form a patterned top layer. The method includes patterning the middle layer by using the patterned top layer as a mask to form a patterned middle layer. The method includes patterning the bottom layer to form a patterned bottom layer. The method also includes removing the patterned middle layer by a base solution, and the middle layer is soluble in the base solution by the hydrophilic group.

Abstract: Some embodiments relate to a die that has been formed by improved dicing techniques. The die includes a substrate which includes upper and lower substrate surfaces with a vertical substrate sidewall extending therebetween. The vertical substrate sidewall corresponds to an outermost edge of the substrate. A device layer is arranged over the upper substrate surface. A crack stop is arranged over an upper surface of the device layer and has an outer perimeter that is spaced apart laterally from the vertical substrate sidewall. The die exhibits a tapered sidewall extending downward through at least a portion of the device layer to meet the vertical substrate sidewall.

Abstract: Provided is a lateral insulated-gate bipolar transistor (LIGBT), comprising a substrate (10), an anode terminal and a cathode terminal on the substrate (10), and a drift region (30) and a gate (61) located between the anode terminal and the cathode terminal. The anode terminal comprises a P-type buried layer (52) on the substrate (10), an N-type buffer region (54) on the P-type buried layer (52), and a P+ collector region (56) on the surface of the N-type buffer region (54). The LIGBT further comprises a trench gate adjacent to the anode terminal, wherein the trench gate penetrates from the surfaces of the N-type buffer region (54) and the P+ collector region (56) to the P-type buried layer (52), and the trench gate comprises an oxidation layer (51) on the inner surface of a trench and polysilicon (53) filled into the oxidation layer.

Abstract: An object is to provide a semiconductor device having a structure in which parasitic capacitance between wirings can be efficiently reduced. In a bottom gate thin film transistor using an oxide semiconductor layer, an oxide insulating layer used as a channel protection layer is formed above and in contact with part of the oxide semiconductor layer overlapping with a gate electrode layer, and at the same time an oxide insulating layer covering a peripheral portion (including a side surface) of the stacked oxide semiconductor layer is formed. Further, a source electrode layer and a drain electrode layer are formed in a manner such that they do not overlap with the channel protection layer. Thus, a structure in which an insulating layer over the source electrode layer and the drain electrode layer is in contact with the oxide semiconductor layer is provided.

Abstract: According to the present disclosure, optoelectronic semiconductor chip includes at least one n-doped semiconductor layer, at least one p-doped semiconductor layer and one active layer arranged between the at least one n-doped semiconductor layer and the at least one p-doped semiconductor layer. The p-doped semiconductor layer is electrically contacted by means of a first metallic connection layer, and a reflection-enhancing dielectric layer sequence is arranged between the p-doped semiconductor layer and the first connection layer, which dielectric layer sequence includes a plurality of dielectric layers with different refractive indices.

Abstract: A semiconductor device is disclosed, which includes: at least one device layer being a crystallized layer for example including: a superlattice layer and/or a layer of group III-V semiconductor materials; and a passivation structure comprising one or more layers wherein at least one layer of the passivation structure is a passivation layer grown in-situ in a crystallized form on top of the device layer, and at least one of the one or more layers of the passivation structure includes material having a high density of surface states which forces surface pinning of an equilibrium Fermi level within a certain band gap of the device layer, away from its conduction and valence bands.

Abstract: A double magnetic tunnel junction (DMTJ) device includes a fixed reference layer of a first magnetic material having a perpendicular magnetic anisotropy with a magnetic moment that is fixed. The device also includes a free layer of a second magnetic material having a perpendicular magnetic anisotropy with a magnetic moment that is changeable based on a current. A dynamic reference layer of a third magnetic material has an in-plane magnetic anisotropy and a changeable magnetic moment. The free layer is disposed between the fixed reference layer and the dynamic reference layer.