Abstract: The present invention is a silicon single crystal substrate for a solid-state image sensor obtained by slicing a silicon single crystal fabricated by a CZ method, where the silicon single crystal substrate is a p-type silicon single crystal substrate whose main dopant is Ga, and the silicon single crystal substrate has a B concentration of 5×1014 atoms/cm3 or less. This provides a silicon single crystal substrate and a silicon epitaxial wafer for a solid-state image sensor that can suppress the residual image characteristics of a solid-state image sensor.

Abstract: A pointed-trench pixel-array substrate includes a floating diffusion region and a photodiode region formed in a semiconductor substrate. The semiconductor substrate includes, between a top surface and a back surface thereof, a sidewall surface and a bottom surface defining a trench extending into the semiconductor substrate away from a planar region of the top surface surrounding the trench. In a cross-sectional plane perpendicular to the top surface and intersecting the floating diffusion region, the photodiode region, and the trench, (i) the bottom surface is V-shaped and (ii) the trench is located between the floating diffusion region and the photodiode region.

Abstract: A semiconductor device includes a P-type Field Effect Transistor (PFET) and an NFET. The PFET includes an N-well disposed in a substrate, a first fin structure disposed over the N-well, a first liner layer disposed over the N-well, and a second liner layer disposed over the first liner layer. The first liner layer and the second liner layer include different materials. The NFET includes a P-well disposed in the substrate, a second fin structure disposed over the P-well, a third liner layer disposed over the P-well. The third liner layer and the second liner layer include the same materials.

Abstract: A semiconductor structure includes a first nanosheet fin extending vertically from a first region of a substrate corresponding to a logic device and a second nanosheet fin extending vertically from a second region of the substrate corresponding to an input/output device. The first nanosheet fin includes first semiconductor channel layers vertically stacked over the first region of the substrate, while the second nanosheet fin includes an alternating sequence of semiconductor sacrificial layers and second semiconductor channel layers. The semiconductor structure further includes an epitaxially grown encapsulation layer disposed only along sidewalls of the second nanosheet fin.

Abstract: A display device includes: a substrate including a display area and a non-display area; and a plurality of sub-pixels arranged in the display area and including portions of an electrode disposed over the display area. The plurality of sub-pixels includes a first sub-pixel and a second sub-pixel to emit light of the same color, a first portion of the electrode of the first sub-pixel has a thickness different from a thickness of a second portion of the electrode of the second sub-pixel, and the first sub-pixel has a size different from a size of the second sub-pixel.

Abstract: A semiconductor device, the device including: a first silicon layer including a first single crystal silicon layer; a first metal layer disposed over the first single crystal silicon layer; a second metal layer disposed over the first metal layer; a third metal layer disposed over the second metal layer; a second level including a plurality of transistors, the second level disposed over the third metal layer; a fourth metal layer disposed over the second level; a fifth metal layer disposed over the fourth metal layer; and a via disposed through the second level, where the via has a diameter of less than 450 nm, and where a typical thickness of the fifth metal layer is greater than a typical thickness of the third metal layer by at least 50%.

Abstract: A display substrate, a manufacturing method thereof, and a display device are provided. The display substrate includes a base substrate, a driving circuit layer and a light-emitting unit located on the base substrate, the light-emitting unit includes a first and a second electrodes being laminated, a light-emitting layer located therebetween; the display substrate includes a first and a second display regions, an opening region; the second display region is located between the first and the opening display regions; a pixel density of the first display region is greater than that of the second display region; and the display substrate further includes a compensation capacitor for compensating a sub-pixel in the second display region, the compensation capacitor includes a first and second plates, the first plate is electrically connected to the gate electrode of the sub-pixel in the second display region, the second plate is electrically connected to the first electrode.

Abstract: A method of fabricating a cascode amplifier including a common-source device and a common-gate device includes performing one or more of ion implantation of a well of the common-source device, ion implantation of a source extension and/or drain extension of the common-source device, or a halo ion implantation of the common-source device with one or more of a different ionic species, a different dosage, a different energy, or a different tilt angle than a corresponding one or more of ion implantation of a well of the common-gate device, ion implantation of a source and/or drain extension of the common-gate device, or a halo ion implantation of the common-gate device.

Abstract: Disclosed are a display panel and a display device. The display panel includes a base substrate, and a first display region and a second display region that are located on the base substrate, where the first display region includes a plurality of first sub-pixels and a plurality of transparent regions, the second display region includes a plurality of second sub-pixels, and a distribution density of the first sub-pixels is smaller that of the second sub-pixels; and an area occupied by the first sub-pixels is smaller than that occupied by the second sub-pixels.

Abstract: An electrostatic discharge (ESD) protection circuit includes a plurality of transistors each including a gate terminal, a drain terminal, and a source terminal, a first connection line connected to the drain terminals of the plurality of transistors, a second connection line connected to the source terminals of the plurality of transistors, a third connection line connected to the gate terminals of the plurality of transistors, an external resistor connected to the third connection line, and a ground terminal connected to the external resistor. The external resistor includes a first resistor and a second resistor connected to each other in parallel.

Abstract: A method of forming a semiconductor device comprises forming a fin structure; forming a source/drain structure in the fin structure; and forming a gate electrode over the fin structure. The source/drain structure includes Si1?x?yM1xM2y, where M1 includes Sn, M2 is one or more of P and As, 0.01?x?0.1, and 0.01?y?0.

Abstract: An electronic panel, includes: a base substrate including a front surface, a rear surface opposite the front surface, and a plurality of side surfaces connecting the front surface and the rear surface to each other; a pixel definition layer on the front surface of the base substrate and having a plurality of openings defined therein; a plurality of emitting elements in the openings; and a spacer on the pixel definition layer and spaced apart from the openings, wherein a thickness of the spacer is equal to or greater than a thickness of the pixel definition layer.

Abstract: A weight optimized stiffener for use in a semiconductor device is disclosed herein. In one example, the stiffener is made of AlSiC for its weight and thermal properties. An O-ring provides sealing between a top surface of the stiffener and a component of the semiconductor device and adhesive provides sealing between a bottom surface of the stiffener and another component of the semiconductor device. The stiffener provides warpage control for a lidless package while enabling direct liquid cooling of a chip or substrate.

Abstract: Split ash processes are disclosed to suppress damage to low-dielectric-constant (low-K) layers during via formation. For one embodiment, ash processes used to remove an organic layer, such as an organic planarization layer (OPL), associated with via formation are split into multiple ash process steps that are separated by intervening process steps. A first ash process is performed to remove a portion of an organic layer after vias have been partially opened to a low-K layer. Subsequently, after the vias are fully opened through the low-K layer, an additional ash process is performed to remove the remaining organic material. Although some damage may still occur on via sidewalls due to this split ash processing, the damage is significantly reduced as compared to prior solutions, and device performance is improved. Target critical dimension (CD) for vias and effective dielectric constants for the low-K layer are achieved.

Abstract: Disclosed herein are CdTe-based solar cells that are successfully removed from their glass superstrate through a combination of lamination to a backsheet followed by thermal shock.

Abstract: Embodiments of the present invention are directed to methods and resulting structures for nanosheet devices having defect free channels. In a non-limiting embodiment of the invention, a nanosheet stack is formed over a substrate. The nanosheet stack includes alternating first sacrificial layers and second sacrificial layers. One layer of the first sacrificial layers has a greater thickness than the remaining first sacrificial layers. The first sacrificial layers are removed and semiconductor layers are formed on surfaces of the second sacrificial layers. The semiconductor layers include a first set and a second set of semiconductor layers. The second sacrificial layers are removed and an isolation dielectric is formed between the first set and the second set of semiconductor layers.

Abstract: A semiconductor device includes first cell rows and second cell rows. The first cell rows extend in a first direction. Each of the first cell rows has a first row height. The second cell rows extend in the first direction. Each of the second cell rows has a second row height. The first row height is greater than the second row height. The first cell rows and the second cell rows are interlaced in a periodic sequence. A first row quantity of the first cell rows in the periodic sequence is greater than a second row quantity of the second cell rows in the periodic sequence.

Abstract: The present disclosure provides a manufacturing method of a display substrate, a display substrate and a display device, belongs to the field of display technology, and can at least partially solve a problem of residual sand in the display substrate. The manufacturing method of the display substrate includes: providing a base; forming a passivation layer on a surface of the base; forming an amorphous oxide conductive material layer on a surface of the passivation layer facing away from the base; forming a photoresist pattern on the oxide conductive material layer, the photoresist pattern having an exposure region; etching a portion of the oxide conductive material layer in the exposure region of the photoresist pattern to form a hollow position exposing a portion of the passivation layer; and removing a certain thickness material of the portion of the passivation layer exposed through the hollow position.

Abstract: A memory device, a semiconductor device and a manufacturing method of the memory device are provided. The memory device includes first, second and third stacking structures, first and second channel structures, a gate dielectric layer, a switching layer, and first and second gate structures. The first, second and third stacking structures are laterally spaced apart from one another, and respectively comprise a conductive layer, an isolation layer and a channel layer. The third stacking structure is located between the first and second stacking structures. The first channel structure extends between the channel layers in the first and third stacking structures. The second channel structure extends between the channel layers in the second and third stacking structures. The gate dielectric layer and the first gate structure wrap around the first channel structure. The switching layer and the second gate structure wrap around the second channel structure.

Abstract: A method for fabricating p-type field effect transistor (FET) includes the steps of first providing a substrate, forming a pad layer on the substrate, forming a well in the substrate, performing an ion implantation process to implant germanium ions into the substrate to form a channel region, and then conducting an anneal process to divide the channel region into a top portion and a bottom portion. After removing the pad layer, a gate structure is formed on the substrate and a lightly doped drain (LDD) is formed adjacent to two sides of the gate structure.