Patents Examined by Norman Michael Wright
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Patent number: 6088817Abstract: A fault tolerant queue system for selecting storing positions in a memory for performing write operations from an on-line maintained idle list of addresses to free storing positions in the memory and for calculating addresses for collecting data earlier stored in the memory. The storing positions are exposed to a testing procedure. The testing procedure is performed periodically on each storing position in idle cycles during operation of the system, and the result is used to maintain the idle list. The addresses selected for testing are released from system use as controlled by the system.Type: GrantFiled: November 4, 1997Date of Patent: July 11, 2000Assignee: Telefonaktiebolaget LM EricssonInventor: Tord Lennart Haulin
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Patent number: 6079031Abstract: An error detection mechanism for detecting programming errors in a computer program. A component of the computer program, e.g., a procedure or function of the computer program, is analyzed to determine the effect of the component on resources used by the computer program. A component is analyzed by traversing the computer instructions, i.e., statements, of the component and tracking the state of resources used by the component as affected by the statements of the component. Each resource has a prescribed behavior represented by a number of states and transition between states. Violations in the prescribed behavior of a resource resulting from an emulated execution of the statements of the component are detected and reported as programming errors. Resources used by two or more components are modelled by modelling externals of the components.Type: GrantFiled: August 1, 1997Date of Patent: June 20, 2000Assignee: Microsoft CorporationInventors: Matthew A. Haley, Jonathan D. Pincus, William R. Bush
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Patent number: 6067634Abstract: A system for recovering resources, wherein the system includes a plurality of allocating services that each allocate resources to clients and a resource audit service in communication with each of the plurality of allocating services. When one of the plurality of allocating services allocates a resource to a client, the one of the plurality of allocating services sends a registration to the resource audit service identifying the client as a recipient of the resource. The resource audit service monitors status of the clients thereby freeing the plurality of allocating services from individually monitoring the status of the clients to which resources have been allocated. When one of the clients fails, the resource audit service sends a failure notification to each of the plurality of allocating services that have allocated a resource to the failed client, thereby allowing each of the plurality of allocating services to recover the resource that had been allocated to the failed client.Type: GrantFiled: July 24, 1998Date of Patent: May 23, 2000Assignee: Silicon Graphics, Inc.Inventor: Michael N. Nelson
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Patent number: 6064804Abstract: A battery, usable with one or more battery support units and/or electronic devices, contains a memory which contains a mailbox. The battery receives a request from a battery support unit or an electronic device to write error data in the mailbox. In response to this request, the battery stores the error data in the mailbox. The battery then receives a request from a battery support unit or electronic device to read the error data from the mailbox. In response to this request, the battery transmits the error data to the battery support unit or electronic device that requested it.Type: GrantFiled: May 23, 1997Date of Patent: May 16, 2000Assignee: Hewlett-Packard CompanyInventors: Gregory D. Brink, Carl E. Benvegar, Dennis E. Ochs, Jonathan N. Andrews
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Patent number: 6065137Abstract: A network analyzer measurement method adaptively adjusts measurement parameters of the network analyzer, based on a set of measurements of a device under test (DUT) and according to a user-specified limit contour, maximum permissible measurement error or other decision criteria. Measurement speed of the network analyzer is optimized by performing subsequent measurements on the DUT using the adjusted measurement parameters. Measurement bandwidth, the number of measurement sweeps or the frequency location of stimulus points of the analyzer is optimized when characterizing the DUT.Type: GrantFiled: April 6, 1998Date of Patent: May 16, 2000Assignee: Hewlett-Packard CompanyInventors: Joel P. Dunsmore, Michael S. Marzalek, Susan Wood
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Patent number: 6061796Abstract: A virtual private network for communicating between a server and clients over an open network uses an applications level encryption and mutual authentication program and at least one shim positioned above either the socket, transport driver interface, or network interface layers of a client computer to intercept function calls, requests for service, or data packets in order to communicate with the server and authenticate the parties to a communication and enable the parties to the communication to establish a common session key. Where the parties to the communication are peer-to-peer applications, the intercepted function calls, requests for service, or data packets include the destination address of the peer application, which is supplied to the server so that the server can authenticate the peer and enable the peer to decrypt further direct peer-to-peer communications.Type: GrantFiled: August 26, 1997Date of Patent: May 9, 2000Assignee: V-One CorporationInventors: James F. Chen, Jieh-Shan Wang, Christopher T. Brook, Francis Garvey
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Patent number: 6058490Abstract: A method and an apparatus for providing scalable layers of highly available applications using loosely coupled commercially available computers. The software running on the loosely coupled computers is divided into three layers: the system layer, the platform layer, and the application layer, each having its own process group activation and fault recovery strategy. A process group contains software processes that depend upon a set of resources common to the process group. In addition to depending upon a common set of resources, processes within a process group share a fault recovery strategy. Fault recovery is performed at the process group level, such that if one process within a process group fails, fault recovery is takes place for all processes within the process group. In the preferred embodiment, an application layer process group may be paired with another application layer process group on a separate computer.Type: GrantFiled: April 21, 1998Date of Patent: May 2, 2000Assignee: Lucent Technologies, Inc.Inventors: Reginald L. Allen, Debra K. Haddad, Susan A. Lee, John H. Pokropinski, Bonnie L. Prokopowicz, Dale F. Rathunde, James P. Schoonover, Raymond D. Smith
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Patent number: 6058491Abstract: A method and system for handling detected faults in a processor to improve reliability of a computer system is disclosed. A fault-tolerant computer system is provided which includes a first processor, a second processor, and a comparator. Coupled to a system bus, a first processor is utilized to produce a first output. The second processor, also coupled to the system bus, is utilized to produce a second output. During the operation of the computer system, the second processor operates at the same clock speed as the first processor and lags behind the first processor. The comparator is utilized to compare the first and second output such that an operation will be retried if the first output is not the same as the second output.Type: GrantFiled: September 15, 1997Date of Patent: May 2, 2000Assignee: International Business Machines CorporationInventors: Douglas Craig Bossen, Arun Chandra
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Patent number: 6052795Abstract: In an external storage, an I/O process continues without any intervention of a user of a host system upon failure of a controller. When a failure occurs in a controller, a host system recognizes the failure of the controller. Before the failure is notified to the user and application program to stop the job, the substitute controller reads the SCSI-ID possessed by an SCSI port of the failed controller from a shared memory, registers the SCSI-ID of the SCSI port to the SCSI port associated with the substitute controller, and erases by a port address resetting facility of the substitute controller the SCSI-ID possessed by an SCSI port of the failed controller. Due to such provision, since the SCSI-ID specified at issuance of an I/O request is transferred between the controllers, the user or the host system need not alter the I/O request issuing route.Type: GrantFiled: October 29, 1996Date of Patent: April 18, 2000Assignee: Hitachi, Ltd.Inventors: Akira Murotani, Toshio Nakano, Hidehiko Iwasaki, Kenji Muraoka
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Patent number: 6052797Abstract: Two data storage systems are interconnected by a data link for remote mirroring of data. Each volume of data is configured as local, primary in a remotely mirrored volume pair, or secondary in a remotely mirrored volume pair. Normally, a host computer directly accesses either a local or a primary volume, and data written to a primary volume is automatically sent over the link to a corresponding secondary volume. Each remotely mirrored volume pair can operate in a selected synchronization mode including synchronous, semi-synchronous, adaptive copy--remote write pending, and adaptive copy--disk. Each write request transmitted over the link between the data storage systems includes not only the data for at least one track in the secondary volume to be updated but also the current "invalid track" count for the secondary volume as computed by the data storage system containing the corresponding primary volume.Type: GrantFiled: August 20, 1998Date of Patent: April 18, 2000Assignee: EMC CorporationInventors: Yuval Ofek, Natan Vishlitzky, Haim Kopylovitz
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Patent number: 6052788Abstract: The present invention, generally speaking, provides a firewall that achieves maximum network security and maximum user convenience. The firewall employs "envoys" that exhibit the security robustness of prior-art proxies and the transparency and ease-of-use of prior-art packet filters, combining the best of both worlds. No traffic can pass through the firewall unless the firewall has established an envoy for that traffic. Both connection-oriented (e.g., TCP) and connectionless (e.g., UDP-based) services may be handled using envoys. Establishment of an envoy may be subjected to a myriad of tests to "qualify" the user, the requested communication, or both. Therefore, a high level of security may be achieved. The usual added burden of prior-art proxy systems is avoided in such a way as to achieve full transparency--the user can use standard applications and need not even know of the existence of the firewall. To achieve full transparency, the firewall is configured as two or more sets of virtual hosts.Type: GrantFiled: April 26, 1999Date of Patent: April 18, 2000Assignee: Network Engineering Software, Inc.Inventors: Ralph E. Wesinger, Jr., Christopher D. Coley
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Patent number: 6047387Abstract: A system implement simulation system's capable of facilitating integrated circuit designers to perform a complete integrated circuit testing with respect to a target peripheral device and demonstrate various functions and their sequence of operations without having to build the target device physically. The system allows, reliability and quality of an integrated circuit design to be increased, and production and testing costs can be reduced. The simulation system is capable of performing functional checking at any time, and can be utilized in demonstrating product functions to customer.Type: GrantFiled: March 20, 1998Date of Patent: April 4, 2000Assignee: Winbond Electronics Corp.Inventors: Alber Chang, Crystal Chu, Jyh-Hwang Wang
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Patent number: 6047392Abstract: A system and method for tracking dirty memory which, in one embodiment, comprises a first memory corresponding to a first processor, a second memory corresponding to a second processor and a third memory coupled to the first memory, wherein the third memory stores bits corresponding to the pages of the first memory, and wherein each bit is set to "dirty" when the first processor writes to the corresponding page of the first memory and is set to "clean" when the corresponding page of the first memory is copied to a corresponding page of the second memory. The system and method can be used in a computer having multiple cpusets to assist in cpuset re-integration by copying the contents of one cpuset's memory to another cpuset's memory while the operating system of the computer continues to run.Type: GrantFiled: March 22, 1999Date of Patent: April 4, 2000Assignee: Sun Microsystems, Inc.Inventors: David C. Liddell, Emrys J. Williams
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Patent number: 6047385Abstract: Full restoration of a telecommunications network element (12), such as a digital cross-connect system (DCS), is accomplished by receiving from each element provisioning updates as they occur in real time via a local controller network (18). The provisioning changes are stored, typically via a local controller library (20). A DCS-OSS data base (22) creates and stores restoration maps for each DCS and, in response to updates from the local controller library 20, the DCS-OSS data base updates the stored restoration maps. Should a DCS become inoperative, that DCS can be restored (either by itself, or on another DCS) using the restoration map. Since the map contains the most up-to-date data, full restoration can be readily achieved.Type: GrantFiled: September 10, 1997Date of Patent: April 4, 2000Assignee: AT&T CorpInventors: Richard L. Guzman, Ihor J. B. Wynarczuk
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Patent number: 6047386Abstract: An apparatus for allowing a RAM array within an SRAM to be tested via scan ATPG is disclosed. A first clocked flip-flop has a data input latched high, a scan-in input latched high, a clock input coupled to a signal source generating a periodic waveform, a scan-enable input coupled to a scan enable signal, and an output. The first flip-flop inverts the data input at the output when the scan enable signal is low, and places the scan-in input signal at the output when the scan enable signal is high. A second clocked flip-flop has a data input coupled to the output of the first flip-flop, a scan-in input latched high, a clock input coupled to the signal source, a scan enable input coupled to the scan enable signal, and an output. The second flip-flop inverts the data input at the output when the scan enable signal is low, and places the scan-in input signal at the output when the scan enable signal is high.Type: GrantFiled: November 5, 1998Date of Patent: April 4, 2000Assignee: Sun Microsystems, Inc.Inventors: Amit D. Sanghani, Narayanan Sridhar
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Patent number: 6041411Abstract: A method for minimizing the potential for unauthorized use of digital information, particularly software programs, digital content and other computer information, by verifying user access rights to electronically transmitted digital information. A second computer system transmits requested digital information to a requesting first computing system in wrapped form, which includes digital instructions that must be successfully executed, or unwrapped, before access to the digital information is allowed. Successful unwrapping requires that certain conditions must be verified in accordance with the digital instructions, thereby allowing access to the digital information. In one embodiment, verification includes locking the digital information to the requesting computer system by comparing a generated digital fingerprint associated with the digital information to a digital fingerprint previously generated which is unique to the requesting computer system.Type: GrantFiled: March 28, 1997Date of Patent: March 21, 2000Inventor: Stuart Alan Wyatt
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Patent number: 6038677Abstract: A method and apparatus that automatically generates and maintains resource groups for a clustered computer network configuration. Resource groups are said to be generated "automatically" because the system administrator preferably is not directly involved with defining what resources go within a particular group. Rather, the administrator merely identifies a set of resources that must be collocated with a given application in the event of a failure of a computer on which the application is then executing. One or more resource groups are then automatically generated using a set of collocation "constraints" or rules. A first collocation constraint preferably enforces any user-defined collocations for a given application, and a second constraint collocates disk partition resources residing on the same physical disk. A resource group generated is this manner ensures effective fault-tolerant operation.Type: GrantFiled: March 31, 1997Date of Patent: March 14, 2000Assignee: International Business Machines CorporationInventors: Francis D. Lawlor, James Wendell Arendt, Hovey Raymond Strong
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Patent number: 6038682Abstract: A data processing system containing a monolithic network of cells with sufficient redundancy provided through direct logical replacement of defective cells by spare cells to allow a large monolithic array of cells without uncorrectable defects to be organized, where the cells have a variety of useful properties. The data processing system according to the present invention overcomes the chip-size limit and off-chip connection bottlenecks of chip-based architectures, the von Neumann bottleneck of uniprocessor architectures, the memory and I/O bottlenecks of parallel processing architectures, and the input bandwidth bottleneck of high-resolution displays, and supports integration of up to an entire massively parallel data processing system into a single monolithic entity.Type: GrantFiled: March 19, 1997Date of Patent: March 14, 2000Assignee: Hyperchip Inc.Inventor: Richard S. Norman
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Patent number: 6038681Abstract: A multi-array disk apparatus includes first and second logical drives, a first array controller, a second array controller, and interface control circuits. Each of the first and second logical drives has two logical structure disks constituting a pair. The first array controller controls the first logical drive. The second array controller controls the second logical drive. When a fault occurs in the other of the first and second array controllers, the interface control circuits bus-connect one of the first and second array controller in which no fault occurs to the logical structure disk connected to the other of the first and second array controller in which the fault occurs.Type: GrantFiled: September 3, 1997Date of Patent: March 14, 2000Assignee: NEC CorporationInventor: Takuya Saegusa
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Patent number: 6038667Abstract: A security enhanced computer system arrangement includes a coprocessor and a multiprocessor logic controller inserted into the architecture of a conventional computer system. The coprocessor and multiprocessor logic controller is interposed between the CPU of the conventional computer system to intercept and replace control signals that are passed over certain of the critical control signal lines associated with the CPU. The multiprocessor logic controller arrangement thereby isolates the CPU of the conventional computer system from the remainder of the conventional computer system, permitting separate control over the CPU and separate control over the remainder of the computer system. By controlling the control signals that are normally passed between the CPU and the remainder of the computer system, the multiprocessor logic controller permits the coprocessor to perform highly secure operations.Type: GrantFiled: October 14, 1998Date of Patent: March 14, 2000Inventor: Walter A. Helbig, Sr.