Abstract: Apparatus characterizes the quality of microelectronic features using broadband white light. A highly collimated light source illuminates an area of a first wafer using broadband multi-spectral light. The angular distribution of the light scattered from the first wafer is then measured. Generally, the angle of the light source, detector, or both is altered and an angular distribution measurement taken at each angle, producing a scatter signature for the first wafer. Finally, the scatter signature of the first wafer is compared with a known scatter signature of a second wafer of good quality to determine the quality of the first wafer.

Abstract: A compact and light weight front light, a reflective liquid crystal display device, and a personal digital assistant providing an image display of uniform brightness with high efficiency are provided. The front light includes a main optical guide plate and a second optical guide plate. The second optical guide plate is arranged at an end of the main optical guide plate along the widthwise direction, and, on an end surface opposite an end surface facing the main optical guide plate, grooves forming prisms are aligned along the longitudinal direction, extending in the depth direction. The front light further includes a point light source arranged at an end, in the longitudinal direction, of the second optical guide plate, and a reflective film covering the surfaces of the grooves.

Abstract: Systems and methods are provided for detecting flow in a mass flow controller (MFC). The position of a gate in the MFC is sensed or otherwise determined to monitor flow through the MFC and to immediately or nearly immediately detect a flow failure. In one embodiment of the present invention, a novel MFC is provided. The MFC includes an orifice, a mass flow control gate, an actuator and a gate position sensor. The actuator moves the control gate to control flow through the orifice. The gate position sensor determines the gate position and/or gate movement to monitor flow and immediately or nearly immediately detect a flow failure. According to one embodiment of the present invention, the gate position sensor includes a transmitter for transmitting a signal and a receiver for receiving the signal such that the receiver provides an indication of the position of the gate based on the signal received.

Abstract: A pixel unit included in a multi-domain vertically aligned liquid crystal display is provided. The pixel unit includes a first insulating substrate having a first side and a second side, a second insulating substrate having a third side and a fourth side, a plurality of liquid crystal molecules filled between the first side of the first insulating substrate and the fourth side of the second insulating substrate, an electric field generation device for providing an electric field to change alignment of the liquid crystal molecules, and a cone protrusion formed on the first side of the first insulating substrate for generating an advance inclination of the liquid crystal molecules around the cone protrusion.

Abstract: A silicon oxide layer is produced by plasma enhanced oxidation of an organosilicon compound to deposit films having a carbon content of at least 1% by atomic weight. Films having low moisture content and resistance to cracking are deposited by introducing oxygen into the processing chamber at a flow rate of less than or equal to the flow rate of the organosilicon compounds, and generating a plasma at a power density ranging between 0.9 W/cm2 and about 3.2 W/cm2. An optional carrier gas may be introduced to facilitate the deposition process at a flow rate less than or equal to the flow rate of the organosilicon compounds. The organosilicon compound preferably has 2 or 3 carbon atoms bonded to each silicon atom, such as trimethylsilane, (CH3)3SiH. An oxygen rich surface may be formed adjacent the silicon oxide layer by temporarily increasing oxidation of the organosilicon compound.

Abstract: A method for producing fluorinated hydrogenated silicon oxycarbide (H:F:SiOC) and amorphous fluorinated hydrogenated silicon carbide (H:F:SiC) films having low dielectric permittivity. The method comprises reacting a silicon containing compound with a fluorocarbon or fluorohydrocarbon compound having an unsaturated carbon bonded to F or H. The resulting films are useful in the formation of semiconductor devices.

Abstract: A condenser angle of 0.5 mrad or below is set with respect to a specimen. Electron-beam diameter of 20 to 100 nm &phgr; is set onto the surface of the specimen. A flux of highly parallel electron beams is irradiated onto the specimen having a strained layer quantum well structure. An image of electrons diffracted from the specimen is recorded onto an imaging plate. The recorded image is analyzed. Lattice constants and strains of layers of the strained layer quantum well structure are measured based on a result of this analysis.

Abstract: An apparatus (110) and method for depositing material on a semiconductor wafer with non-planar structures (114). The wafer (114) is positioned in a chamber (111), and reactive gases (132) are introduced into the chamber (111). The gases (132) and wafer (114) are heated, wherein the gas (132) temperature in the process chamber (111) and in the vicinity of the wafer (114) surface is lower than the temperature of the wafer (114) surface. A material is deposited on the wafer (114) surface using chemical vapor deposition. A gas cooler may be utilized to lower the temperature of the reactive gases (132) while the wafer (114) is heated.

Abstract: A method for moving resist stripper across the surface of a semiconductor substrate. The method includes applying a wet chemical resist stripper, such as an organic or oxidizing wet chemical resist stripper, to at least a portion of a photomask positioned over the semiconductor substrate. A carrier fluid, such as a gas, is then directed toward the semiconductor substrate so as to move the resist stripper across the substrate. The carrier fluid may be directed toward the substrate as the resist stripper is being applied thereto or following application of the resist stripper. A system for effecting the method is also disclosed.

Abstract: Semiconductor device chips manufacturing and inspecting method is disclosed in which a semiconductor wafer is cut into individual LSI chips. The LSI chips are rearranged and integrated into a predetermined number. The cut LSI chips are integrated in a jig having openings with a size commensurate with the dimensions of the LSI chip. At least one part of the jig having such openings has a coefficient of thermal expansion that is approximately equal to that of the LSI chips. The integrated predetermined number of chips are subjected to an inspection process in a subsequent inspection step thereby improving efficiency and reducing cost.

Abstract: Provided is a method for fabricating a compound semiconductor multilayer epitaxial substrate comprising a plurality of epitaxial layers, comprising the steps of determining at least one of the thickness, impurity concentration, and composition of an epitaxial layer comprising the multilayer epitaxial substrate by theoretical calculation, the theoretical calculation describing on electric field and charge distribution inside the epitaxial layer, and performing epitaxy of the epitaxial layer according to the theoretical calculation of the thickness, impurity concentration and/or composition of the epitaxial layer so that measurable electric characteristics of the substrate predetermined by the calculation are satisfied. The method can reduce the fabrication process and also can be applied to manufacture a multilayer epitaxial substrate having a unique structure.

Abstract: A method is for low-dielectric-constant film deposition on a surface of a semiconductor substrate. The deposition may be by chemical vapor deposition (CVD) techniques and may include a wide class of precursor monomeric compounds, namely organosilanes.

Abstract: Procedures, analysis techniques, and correction methods are presented for assessing the electrical properties of the Si layer of silicon-on-insulator substrates. Detailed analysis and equations are outlined in a computer algorithm written in Mathcad for both the linear and saturated regions of FET behavior.

Abstract: The present invention provides a method of enabling measurement access to small integrated circuit features that comprises selecting a feature of an integrated circuit on a wafer and providing access to the selected feature by removing a portion of the integrated circuit adjacent to the feature, thereby preserving the wafer.

Abstract: A process monitor includes a test circuit formed on a product die wherein the test circuit has a distribution of cell types that is substantially identical to that of the product die.

Abstract: A method of manufacturing a compound layer, containing a nitrified metal as a major component thereof and having a predetermined microstructure pattern, includes: an ion implantation step for implanting hydrogen ions into a predetermined region of a compound layer formed on a substrate to form an implanted region; and an etching step for selectively etching the implanted region by using a gas containing at least oxygen, to remove the implanted region of the compound layer while maintaining the other region as a microstructure pattern. By introducing a halogen element like fluorine in addition to hydrogen, fabrication of the pattern can be executed more reliably and more easily. As a result, volatility of reaction products produced upon etching the compound layer is enhanced, and micro-loading effects are suppressed.

Abstract: A method of forming a SOG insulation layer of a semiconductor device comprises the steps of forming the SOG insulation layer on a substrate having a stepped pattern using a solution containing a polysilazane in an amount of less than 20% by weight in terms concentration of solid content, performing a pre-bake process for removing solvent ingredients in the insulation layer at a temperature of 50 to 350° C., and annealing at a temperature of 600 to 1200° C. The method of the invention further includes performing a hard bake process at a temperature of about 400° C. between the pre-bake process and the annealing step. Also, the polysilazane is desirably contained in an amount of 10 to 15% by weight.

Abstract: Semiconductor device chips manufacturing and inspecting method is disclosed in which a semiconductor wafer is cut into individual LSI chips. The LSI chips are rearranged and integrated into a predetermined number. The cut LSI chips are integrated in a jig having openings with a size commensurate with the dimensions of the LSI chip. At least one part of the jig having such openings has a coefficient of thermal expansion that is approximately equal to that of the LSI chips. The integrated predetermined number of chips are subjected to an inspection process in a subsequent inspection step thereby improving efficiency and reducing cost.

Abstract: A semiconductor device structure and process for its fabrication includes a first layer of HDP oxide and an overlying layer of silicon oxynitride. Application of the HDP oxide to a pattern of metal structures fills gaps between the metal structures and allows for the void free deposition of the silicon oxynitride layer. The silicon oxynitride layer provides a hard outer coating to the passivation coating and is UV transparent so that, if necessary, non-volatile floating gate memory devices can be UV erased.

Abstract: A method and an apparatus for preparing a backside-ground wafer for testing are described. The method includes the steps of first providing a calibration wafer that has a pattern formed on a top surface of an insulating material such as oxide or nitride. Three droplets of water are applied with each droplet sufficiently apart from the other droplets on the top surface of the calibration wafer. A backside-ground wafer that has a ground backside and a front side to be tested is then mated to the calibration wafer by mating the ground backside to the top surface of the calibration wafer with water droplets therein-between forming a bond by capillary reaction in-between the oxide pattern on the calibration wafer. The apparatus for mounting a backside-ground wafer to a calibration wafer consists of a slanted block having a top surface with a slant angle between about 10° and about 30°.