Patents Examined by Ori Nadav
  • Patent number: 10269863
    Abstract: Methods for forming via last through-vias. A method includes providing an active device wafer having a front side including conductive interconnect material disposed in dielectric layers and having an opposing back side; providing a carrier wafer having through vias filled with an oxide extending from a first surface of the carrier wafer to a second surface of the carrier wafer; bonding the front side of the active device wafer to the second surface of the carrier wafer; etching the oxide in the through vias in the carrier wafer to form through oxide vias; and depositing conductor material into the through oxide vias to form conductors that extend to the active carrier wafer and make electrical contact to the conductive interconnect material. An apparatus includes a carrier wafer with through oxide vias extending through the carrier wafer to an active device wafer bonded to the carrier wafer.
    Type: Grant
    Filed: November 15, 2012
    Date of Patent: April 23, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Szu-Ying Chen, Pao-Tung Chen, Dun-Nian Yaung, Jen-Cheng Liu
  • Patent number: 10265646
    Abstract: The present teachings provide methods for sorting nanotubes according to their wall number, and optionally further in terms of their diameter, electronic type, and/or chirality. Also provided are highly enriched nanotube populations provided thereby and articles of manufacture including such populations.
    Type: Grant
    Filed: February 18, 2015
    Date of Patent: April 23, 2019
    Assignee: NORTHWESTERN UNIVERSITY
    Inventors: Alexander A. Green, Mark C. Hersam
  • Patent number: 10263149
    Abstract: The present invention relates to nanostructured light emitting diodes, LEDs. The nanostructure LED device according to the invention comprises an array of a plurality of individual nanostructured LEDs. Each of the nanostructured LEDs has an active region wherein light is produced. The nanostructured device further comprise a plurality of reflectors, each associated to one individual nanostructured LED (or a group of nanostructured LEDs. The individual reflectors has a concave surface facing the active region of the respective individual nanostructured LED or active regions of group of nanostructured LEDs.
    Type: Grant
    Filed: March 20, 2015
    Date of Patent: April 16, 2019
    Assignee: QUNANO AB
    Inventors: Lars Ivar Samuelson, Bo Pedersen, Bjorn Jonas Ohlsson, Yourii Martynov, Steven L. Konsek, Peter Jesper Hanberg
  • Patent number: 10263117
    Abstract: A semiconductor device having favorable electric characteristics is provided. An oxide semiconductor layer includes first and second regions apart from each other, a third region which is between the first and second regions and overlaps with a gate electrode layer with a gate insulating film provided therebetween, a fourth region between the first and third regions, and a fifth region between the second and third regions. A source electrode layer includes first and second conductive layers. A drain electrode layer includes third and fourth conductive layers. The first conductive layer is formed only over the first region. The second conductive layer is in contact with an insulating layer, the first conductive layer, and the first region. The third conductive layer is formed only over the second region. The fourth conductive layer is in contact with the insulating layer, the third conductive layer, and the second region.
    Type: Grant
    Filed: January 21, 2015
    Date of Patent: April 16, 2019
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Daigo Ito, Kazuya Hanaoka
  • Patent number: 10256146
    Abstract: A semiconductor device and method of forming the same, the semiconductor device includes a first and second fin shaped structures, a first and second gate structures and a first and second plugs. The first and second fin shaped structures are disposed on a first region and a second region of a substrate and the first and second gate structure are disposed across the first and second fin shaped structures, respectively. A dielectric layer is disposed on the substrate, covering the first and second gate structure. The first and second plugs are disposed in the dielectric layer, wherein the first plug is electrically connected first source/drain regions adjacent to the first gate structure and contacts sidewalls of the first gate structure, and the second plug is electrically connected to second source/drain regions adjacent to the second gate structure and not contacting sidewalls of the second gate structure.
    Type: Grant
    Filed: January 14, 2018
    Date of Patent: April 9, 2019
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Yu-Hsiang Hung, Ssu-I Fu, Chao-Hung Lin, Chih-Kai Hsu, Jyh-Shyang Jenq
  • Patent number: 10249588
    Abstract: Methods, techniques, and structures relating to die packaging. In one exemplary implementation, a die package interconnect structure includes a semiconductor substrate and a first conducting layer in contact with the semiconductor substrate. The first conducting layer may include a base layer metal. The base layer metal may include Cu. The exemplary implementation may also include a diffusion barrier in contact with the first conducting layer and a wetting layer on top of the diffusion barrier. A bump layer may reside on top of the wetting layer, in which the bump layer may include Sn, and Sn may be electroplated. The diffusion barrier may be electroless and may be adapted to prevent Cu and Sn from diffusing through the diffusion barrier. Furthermore, the diffusion barrier may be further adapted to suppress a whisker-type formation in the bump layer.
    Type: Grant
    Filed: December 5, 2016
    Date of Patent: April 2, 2019
    Assignee: Intel Corporation
    Inventors: Valery M. Dubin, Sridhar Balakrishnan, Mark Bohr
  • Patent number: 10236381
    Abstract: A method of manufacturing an integrated circuit is provided. According to the method, a layered fin including a plurality of sacrificial layers and semiconductor layers wherein two adjacent semiconductor layers are separated by the sacrificial layer is provided on a semiconductor substrate. A gate over the layered fin and a spacer surrounding a sidewall of the gate are then formed. The sacrificial layers are subsequently removed to provide a structure in which two adjacent semiconductor layers are separated by a gap. The method further includes forming an insulator in the gap and forming source and drain regions located on the layered fin. The insulator includes a high-K dielectric material surrounded by a low-K dielectric material, both of which are in contact with the two adjacent semiconductor layers.
    Type: Grant
    Filed: May 30, 2017
    Date of Patent: March 19, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kangguo Cheng, Juntao Li, Geng Wang, Qintao Zhang
  • Patent number: 10236303
    Abstract: A protective circuit includes a non-linear element, which includes a gate electrode, a gate insulating layer covering the gate electrode, a pair of first and second wiring layers whose end portions overlap with the gate electrode over the gate insulating layer and in which a second oxide semiconductor layer and a conductive layer are stacked, and a first oxide semiconductor layer which overlaps with at least the gate electrode and which is in contact with the gate insulating layer, side face portions and part of top face portions of the conductive layer and side face portions of the second oxide semiconductor layer in the first wiring layer and the second wiring layer. Over the gate insulating layer, oxide semiconductor layers with different properties are bonded to each other, whereby stable operation can be performed as compared with Schottky junction. Thus, the junction leakage can be decreased and the characteristics of the non-linear element can be improved.
    Type: Grant
    Filed: May 29, 2014
    Date of Patent: March 19, 2019
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Kengo Akimoto, Shigeki Komori, Hideki Uochi, Tomoya Futamura, Takahiro Kasahara
  • Patent number: 10229995
    Abstract: A method of fabricating a fin structure with tensile stress includes providing a structure divided into an N-type transistor region and a P-type transistor region. Next, two first trenches and two second trenches are formed in the substrate. The first trenches define a fin structure. The second trenches segment the first trenches and the fin. Later, a flowable chemical vapor deposition is performed to form a silicon oxide layer filling the first trenches and the second trenches. Then, a patterned mask is formed only within the N-type transistor region. The patterned mask only covers the silicon oxide layer in the second trenches. Subsequently, part of the silicon oxide layer is removed to make the exposed silicon oxide layer lower than the top surface of the fin structure by taking the patterned mask as a mask. Finally, the patterned mask is removed.
    Type: Grant
    Filed: August 4, 2017
    Date of Patent: March 12, 2019
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Kai-Lin Lee, Zhi-Cheng Lee, Wei-Jen Chen, Ting-Hsuan Kang, Ren-Yu He, Hung-Wen Huang, Chi-Hsiao Chen, Hao-Hsiang Yang, An-Shih Shih, Chuang-Han Hsieh
  • Patent number: 10229937
    Abstract: An array structure and a manufacturing method thereof are disclosed. The method for manufacturing the array structure includes: forming a gate insulating layer on a glass substrate; and etching the gate insulating layer at a position corresponding to a source/drain signal access terminal, and forming a through-hole structure provided with an outward-inclined side wall in the gate insulating layer. Conductive films in the source/drain signal access terminal and a gate signal access terminal which have wires thereof alternate with each other have a same height, so that the forces applied to conductive balls can be more uniform, and hence the conductivity can be improved.
    Type: Grant
    Filed: June 20, 2014
    Date of Patent: March 12, 2019
    Assignees: BOE Technology Group Co., Ltd., Beijing BOE Optoelectronics Technology Co., Ltd.
    Inventors: Dawei Shi, Xinyou Ji, Fuqiang Li, Jian Guo
  • Patent number: 10217707
    Abstract: A method is presented for forming a semiconductor device. The method includes forming source/drain over a semiconductor substrate, forming a sacrificial layer over the source/drain, and forming an inter-level dielectric (ILD) layer over the sacrificial layer. The method further includes forming trenches that extend partially into the sacrificial layer, removing the sacrificial layer to expose an upper surface of the source/drain, and filling the trenches with at least one conducting material. The sacrificial layer is germanium (Ge) and the at least one conducting material includes three conducting materials.
    Type: Grant
    Filed: September 16, 2016
    Date of Patent: February 26, 2019
    Assignee: International Business Machines Corporation
    Inventors: Zhenxing Bi, Kangguo Cheng, Juntao Li, Peng Xu
  • Patent number: 10211057
    Abstract: A transistor component includes in a semiconductor body a source zone and a drift zone of a first conduction type, and a body zone of a second conduction type complementary to the first conduction type, the body zone arranged between the drift zone and the source zone. The transistor component further includes a source electrode in contact with the source zone and the body zone, a gate electrode adjacent the body zone and dielectrically insulated from the body zone by a gate dielectric layer, and a diode structure connected between the drift zone and the source electrode. The diode structure includes a first emitter zone adjoining the drift zone in the semiconductor body, and a second emitter zone of the first conduction type adjoining the first emitter zone. The second emitter zone is connected to the source electrode and has an emitter efficiency ? of less than 0.7.
    Type: Grant
    Filed: August 4, 2011
    Date of Patent: February 19, 2019
    Assignee: Infineon Technologies Austria AG
    Inventors: Franz Hirler, Anton Mauder, Thomas Raker, Hans-Joachim Schulze, Wolfgang Werner
  • Patent number: 10211048
    Abstract: A solution for fabricating a semiconductor structure is provided. The semiconductor structure includes a plurality of semiconductor layers grown over a substrate using a set of epitaxial growth periods. During each epitaxial growth period, a first semiconductor layer having one of: a tensile stress or a compressive stress is grown followed by growth of a second semiconductor layer having the other of: the tensile stress or the compressive stress directly on the first semiconductor layer. One or more of a set of growth conditions, a thickness of one or both of the layers, and/or a lattice mismatch between the layers can be configured to create a target level of compressive and/or shear stress within a minimum percentage of the interface between the layers.
    Type: Grant
    Filed: February 1, 2013
    Date of Patent: February 19, 2019
    Assignee: Sensor Electronic Technology, Inc.
    Inventors: Wenhong Sun, Rakesh Jain, Jinwei Yang, Maxim S. Shatalov, Alexander Dobrinsky, Remigijus Gaska, Michael Shur
  • Patent number: 10204990
    Abstract: A semiconductor device includes an N-type silicon carbide substrate, an N-type silicon carbide layer formed on the N-type silicon carbide substrate, a P-type region selectively formed in a surface layer of the N-type silicon carbide layer, an N-type source region formed in the P-type region, a P contact region formed in the P-type region, a gate insulating film formed on a portion of a region from the N-type source region, through the P-type region, to the N-type silicon carbide layer, a gate electrode formed on the gate insulating film, an interlayer insulating film covering the gate electrode, and a first source electrode electrically connected to a surface of the P contact region and the N-type source region. An end of the interlayer insulating film covering the gate electrode has a slope of a predetermined angle.
    Type: Grant
    Filed: September 29, 2016
    Date of Patent: February 12, 2019
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Yuichi Harada, Yasuyuki Hoshi, Akimasa Kinoshita, Yasuhiko Oonishi
  • Patent number: 10196262
    Abstract: A process for manufacturing an interaction system of a microelectromechanical type for a storage medium, the interaction system provided with a supporting element and an interaction element carried by the supporting element, envisages the steps of: providing a wafer of semiconductor material having a substrate with a first type of conductivity (P) and a top surface; forming a first interaction region having a second type of conductivity (N), opposite to the first type of conductivity (P), in a surface portion of the substrate in the proximity of the top surface; and carrying out an electrochemical etch of the substrate starting from the top surface, the etching being selective with respect to the second type of conductivity (N), so as to remove the surface portion of the substrate and separate the first interaction region from the substrate, thus forming the supporting element.
    Type: Grant
    Filed: December 18, 2007
    Date of Patent: February 5, 2019
    Assignee: STMICROELECTRONICS S.R.L.
    Inventors: Giuseppe Barillaro, Alessandro Diligenti, Caterina Riva, Roberto Campedelli, Stefano Losa
  • Patent number: 10186591
    Abstract: A nitride semiconductor device includes: a first nitride semiconductor layer; a second nitride semiconductor layer located on the first nitride semiconductor layer and having a band gap larger than a band gap of the first nitride semiconductor layer; a p-type semiconductor layer located on the second nitride semiconductor layer; and a gate electrode located on the p-type semiconductor layer. A first interface and a second interface are located in parallel between the gate electrode and the p-type semiconductor layer. The first interface has a first barrier with respect to holes moving in a direction from the p-type semiconductor layer to the gate electrode. The second interface has a second barrier with respect to the holes moving in a direction from the p-type semiconductor layer to the gate electrode. The second barrier is higher than the first barrier.
    Type: Grant
    Filed: May 9, 2016
    Date of Patent: January 22, 2019
    Assignee: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventor: Takashi Okawa
  • Patent number: 10170444
    Abstract: Packages for semiconductor devices, packaged semiconductor devices, and methods of packaging semiconductor devices are disclosed. In some embodiments, a package for a semiconductor device includes an integrated circuit die mounting region, a molding material around the integrated circuit die mounting region, and an interconnect structure over the molding material and the integrated circuit die mounting region. The interconnect structure has contact pads, and connectors are coupled to the contact pads. Two or more of the connectors have an alignment feature formed thereon.
    Type: Grant
    Filed: June 30, 2015
    Date of Patent: January 1, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ching-Jung Yang, Yen-Ping Wang
  • Patent number: 10170668
    Abstract: Solid state lighting (“SSL”) devices with improved current spreading and light extraction and associated methods are disclosed herein. In one embodiment, an SSL device includes a solid state emitter (“SSE”) that has a first semiconductor material, a second semiconductor material spaced apart from the first semiconductor material, and an active region between the first and second semiconductor materials. The SSL device can further include a first contact on the first semiconductor material and a second contact on the second semiconductor material and opposite the first contact. The second contact can include one ore more interconnected fingers. Additionally, the SSL device can include an insulative feature extending from the first contact at least partially into the first semiconductor material. The insulative feature can be substantially aligned with the second contact.
    Type: Grant
    Filed: June 21, 2011
    Date of Patent: January 1, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Vladimir Odnoblyudov, Martin F. Schubert
  • Patent number: 10162234
    Abstract: The present invention relates to a display panel and a display module, the display panel comprises a display region and a non-display region, and boundaries between the display region and the non-display region comprise at least one arc structure. The technical effects of the present invention are that it is beneficial to design a display module with an arc and narrow frame, which greatly reduces the range of the frame, increases the area that can be displayed, it is more consistent with the natural display contour of the human eye's physiology, with more comfortable, natural and fantastic display effect.
    Type: Grant
    Filed: November 6, 2013
    Date of Patent: December 25, 2018
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Wenqi Li, Wei Qin
  • Patent number: 10153302
    Abstract: A method for manufacturing a pixel structure is provided. A patterned semiconductor material layer, an insulation material layer, and a gate electrode material layer are formed in sequence on a substrate to form a stacked structure. A patterned photoresist layer is formed on the stacked structure by using a photomask. A portion of the stacked structure is removed to pattern the patterned semiconductor material layer into a patterned semiconductor layer by using the patterned photoresist layer as a mask. Another portion of the stacked structure is etched by using a portion of the patterned photoresist layer as a mask until a portion of the semiconductor layer in the stacked structure is exposed. Then, an exposed portion of the semiconductor layer is modified to increase a conductivity of the exposed portion of the semiconductor layer. Finally, the patterned photoresist layer is removed. A pixel structure manufactured by the method is provided.
    Type: Grant
    Filed: August 18, 2015
    Date of Patent: December 11, 2018
    Assignee: Chunghwa Picture Tubes, Ltd.
    Inventors: Hsi-Ming Chang, Yen-Yu Huang