Abstract: Disclosed is a display apparatus including an LED module having a first fastening member, a front bracket having a second fastening member on which the LED module is mounted by an attractive force generated between the first and second fastening members, and at least one level adjusting member disposed on the LED module and configured to adjust a level difference between the LED module and another adjacent LED module.

Abstract: Some embodiments include apparatuses and methods of forming the apparatuses. One of the apparatuses includes conductive materials located in different levels of the apparatus, dielectric materials located in different levels of the apparatus, a first conductive contact, and a second conductive contact. One of the conductive materials is between two of the dielectric materials. One of the dielectric materials is between two of the conductive materials. The first conductive contact has a length extending through the conductive materials and the dielectric materials in a direction perpendicular to the levels of the apparatus. The first conductive contact is electrically separated from the conductive materials. The second conductive contact contacts a group of conductive materials of the conductive materials.

Abstract: Cubic BAs is used in semiconductors to improve the thermal characteristics of a device. The BAs is used in device layers to improve thermal conductivity. The BAs also provides thermal expansion characteristics that are compatible with other semiconductors and thereby further improves reliability. The substrates of the semiconductors may also include vias that contain BAs. The BAs in the vias may contact the BAs in the device layers. Some vias may have a surface area to volume ratio of greater than 10 to better assist with device heat dissipation.

Abstract: A solid-state imaging device and method of making a solid-state imaging device are described herein. By way of example, the solid-state imaging device includes a first wiring layer formed on a sensor substrate and a second wiring layer formed on a circuit substrate. The sensor substrate is coupled to the circuit substrate, the first wiring layer and the second wiring layer being positioned between the sensor substrate and the circuit substrate. A first electrode is formed on a surface of the first wiring layer, and a second electrode is formed on a surface of the second wiring layer. The first electrode is in electrical contact with the second electrode.

Abstract: A display device includes a plurality of pixels that is arrayed in a first direction and a second direction. Each pixel includes; a first sub-pixel, a second sub-pixel that is disposed to be adjacent to the first sub-pixel in the first direction, a third sub-pixel that is disposed to be adjacent to at least one of the first sub-pixel and the second sub-pixel in the second direction, and a light shielding portion that is disposed corresponding to the position on which the third sub-pixel is disposed, so as to limit a viewing angle of the third sub-pixel in the first direction.

Abstract: An active matrix substrate includes gate bus lines; source bus lines; a lower insulating layer; an oxide semiconductor TFT; and a pixel electrode, in which the oxide semiconductor TFT includes an oxide semiconductor layer disposed on the lower insulating layer, a gate electrode, a source electrode, and a first ohmic conductive portion that is coupled to the oxide semiconductor layer and the source electrode, the lower insulating layer includes a source opening portion exposing at least a portion of the source electrode, the first ohmic conductive portion is disposed on the lower insulating layer and in the source opening portion and is in direct contact with at least the portion of the source electrode in the source opening portion, and the first region of the oxide semiconductor layer is in direct contact with an upper surface of the first ohmic conductive portion.

Abstract: A semiconductor structure having metal contact features and a method for forming the same are provided. The method includes forming a dielectric layer covering an epitaxial structure over a semiconductor substrate and forming an opening in the dielectric layer to expose the epitaxial structure. The method includes forming a metal-containing layer over the dielectric layer and the epitaxial structure. The method includes heating the epitaxial structure and the metal-containing layer to transform a first portion of the metal-containing layer contacting the epitaxial structure into a metal-semiconductor compound layer. The method includes oxidizing the metal-containing layer to transform a second portion of the metal-containing layer over the metal-semiconductor compound layer into a metal oxide layer. The method includes applying a metal chloride-containing etching gas on the metal oxide layer to remove the metal oxide layer and forming a metal contact feature over the metal-semiconductor compound layer.

Abstract: A novel semiconductor device is provided. A back gate voltage of a transistor including a gate and a back gate is adjusted based on the operating temperature. The operating temperature is acquired by a temperature detector circuit. The temperature detection circuit outputs the temperature information as a digital signal. The digital signal is input to a voltage control circuit. The voltage control circuit outputs a first voltage corresponding to the digital signal. The back gate voltage is determined by a voltage in which a first voltage is added to a reference voltage.

Abstract: An electroluminescence display device having a through-hole in a display area is discussed. The electroluminescence display device can include a substrate, a through-hole, an inner dam, and a hole-trench. The substrate includes a display area where a plurality of pixels for displaying images are arranged, and a non-display area surrounding the display area. The through-hole is arranged inside the display area. The inner dam surrounds the through-hole. The hole-trench surrounds the inner dam, and is formed as the substrate is partially recessed as much as a certain thickness.

Abstract: Disclosed herein are quantum dot devices, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include: a gate disposed on a quantum well stack; an insulating material disposed on the gate; and a conductive via extending through the insulating material and in conductive contact with the gate.

Abstract: A structure for preventing deteriorations of a light-emitting device and retaining sufficient capacitor elements (condenser) required by each pixel is provided. A first passivation film, a second metal layer, a flattening film, a barrier film, and a third metal layer are stacked in this order over a transistor. A side face of a first opening provided with the flattening film is covered by the barrier film, a second opening is formed inside the first opening, and a third metal layer is connected to a semiconductor via the first opening and the second opening. A capacitor element that is formed of a lamination of a semiconductor of a transistor, a gate insulating film, a gate electrode, the first passivation film, and the second metal layer is provided.

Abstract: Fin-based well straps are disclosed for improving performance of memory arrays, such as static random access memory arrays. An exemplary integrated circuit (IC) device includes a FinFET disposed over a doped region of a first type dopant. The FinFET includes a first fin having a first width doped with the first type dopant and first source/drain features of a second type dopant. The IC device further includes a fin-based well strap disposed over the doped region of the first type dopant. The fin-based well strap connects the doped region to a voltage. The fin-based well strap includes a second fin having a second width doped with the first type dopant and second source/drain features of the first type dopant. The second width is greater than the first width. For example, a ratio of the second width to the first width is greater than about 1.1 and less than about 1.5.

Abstract: A wiring substrate includes a wiring layer and an insulation layer covering the wiring layer. The insulation layer includes an opening partially exposing the wiring layer. A seed layer continuously covers a wall surface of the opening and an upper surface of the insulation layer. The wiring substrate also includes a metal layer, a metal post, and an outer coating plating layer. The opening is filled with the seed layer and the metal layer formed on the seed layer. The metal post is formed on the metal layer and on the seed layer that is located on the insulation layer. The outer coating plating layer includes an upper portion, entirely covering an upper surface of the metal post, and a side portion, entirely covering a side surface of the metal post and exposing an outer end surface of the seed layer. The side portion is thinner than the upper portion.

Abstract: High voltage semiconductor device and manufacturing method thereof are disclosed. The high voltage semiconductor device includes a semiconductor substrate, a gate structure, at least one first isolation structure and at least one second isolation structure, and at least one first drift region. The gate structure is disposed on the semiconductor substrate. The first isolation structure and the second isolation structure are disposed in an active area of the semiconductor substrate at a side of the gate structure. An end of the second isolation structure is disposed between the first isolation structure and the gate structure, and an end of the first isolation structure is disposed between the first doped region and the second isolation structure. A bottom of the at least one first isolation structure and a bottom of the at least one second isolation structure are deeper than a bottom of the first drift region.

Abstract: This disclosure provides an array substrate and a method of manufacturing the same. The method includes: forming a switch element; etching on an extension of a gate insulation layer to obtain a second amorphous silicon layer, a second N-type amorphous silicon layer and a light sensing metal at the same time to form a photosensor; forming a light sensing layer and a passivation layer on a source metal, a drain metal, and the light sensing metal; and forming a first light sensing layer and a first passivation layer on the source metal and the drain metal, and forming a second light sensing layer and a second passivation layer on the light sensing metal by using a second mask.

Abstract: A semiconductor device includes a substrate, a first FET part and a second FET part disposed on a surface of the substrate. The first FET part includes a first gate electrode region and a first source electrode region spaced apart from each other. The second FET part, connected to the first FET part in a stacked structure, includes a second gate electrode region and a second drain electrode region spaced apart from each other. Each of the first FET part and the second FET part includes a first common electrode and a second common electrode disposed on the surface of the substrate and spaced apart from each other. Each of the first common electrode and the second common electrode is configured to be a single conductor wiring integrally formed by a first drain electrode of the first FET part and a second source electrode of the second FET part.

Abstract: In a method of manufacturing a semiconductor device, a fin structure having a lower fin structure and an upper fin structure disposed over the lower fin structure is formed. The upper fin structure includes first semiconductor layers and second semiconductor layers alternately stacked. The first semiconductor layers are partially etched to reduce widths of the first semiconductor layers. An oxide layer is formed over the upper fin structure. A sacrificial gate structure is formed over the upper fin structure with the oxide layer. A source/drain epitaxial layer is formed over a source/drain region of the fin structure. The sacrificial gate structure is removed to form a gate space. The oxide layer is removed to expose the second semiconductor layers in the gate space. A gate structure is formed around the second semiconductor layers in the gate space.

Abstract: A method is presented for forming a semiconductor device. The method includes forming source/drain over a semiconductor substrate, forming a sacrificial layer over the source/drain, and forming an inter-level dielectric (ILD) layer over the sacrificial layer. The method further includes forming trenches that extend partially into the sacrificial layer, removing the sacrificial layer to expose an upper surface of the source/drain, and filling the trenches with at least one conducting material. The sacrificial layer is germanium (Ge) and the at least one conducting material includes three conducting materials.

Abstract: Packages for semiconductor devices, packaged semiconductor devices, and methods of packaging semiconductor devices are disclosed. In some embodiments, a package for a semiconductor device includes an integrated circuit die mounting region, a molding material around the integrated circuit die mounting region, and an interconnect structure over the molding material and the integrated circuit die mounting region. The interconnect structure has contact pads, and connectors are coupled to the contact pads. Two or more of the connectors have an alignment feature formed thereon.

Abstract: A method for repairing a broken wire, a substrate and a display device are provided. The method is adopted for electrically connecting a first conductive point and a second conductive point separated from each other on a substrate. The method includes: forming a conductive polymer precursor thin film to physically connect the first conductive point and the second conductive point; and performing a polymerizing process on the conductive polymer precursor thin film to form a conductive polymer electrically connecting the first conductive point and the second conductive point.