Patents Examined by Ori Nadav
  • Patent number: 9893071
    Abstract: A semiconductor device and a method for forming the same are disclosed. The semiconductor device includes a semiconductor substrate including an active region defined by a device isolation film, a bit line contact plug that is coupled to the active region and that includes a first ion implantation region buried in a first inner void, and a storage node contact plug that is coupled to the active region and includes a second ion implantation region buried in a second inner void. Although the semiconductor device is highly integrated, a contact plug is buried to prevent formation of a void, so that increase in contact plug resistance is prevented, resulting in improved semiconductor device characteristics.
    Type: Grant
    Filed: February 22, 2016
    Date of Patent: February 13, 2018
    Assignee: SK HYNIX INC.
    Inventors: Jae Soo Kim, Jae Chun Cha
  • Patent number: 9876037
    Abstract: The present invention provides a thin-film transistor array substrate and a manufacturing method thereof. In the thin-film transistor array substrate of the present invention, the portion of the gate insulation layer interposed between two electrode plates of the storage capacitor is smaller than that of the remaining portion of the gate insulation layer so that the thickness of the insulation layer of the storage capacitor is reduced and the area of the opposite surfaces of the capacitor can be made smaller and an increased aperture ratio can be achieved.
    Type: Grant
    Filed: May 25, 2015
    Date of Patent: January 23, 2018
    Assignee: SHENZHEN CHINA STAR OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventors: Xiaowen Lv, Chihyu Su
  • Patent number: 9875911
    Abstract: A semiconductor device has an interposer mounted over a carrier. The interposer includes TSV formed either prior to or after mounting to the carrier. An opening is formed in the interposer. The interposer can have two-level stepped portions with a first vertical conduction path through a first stepped portion and second vertical conduction path through a second stepped portion. A first and second semiconductor die are mounted over the interposer. The second die is disposed within the opening of the interposer. A discrete semiconductor component can be mounted over the interposer. A conductive via can be formed through the second die or encapsulant. An encapsulant is deposited over the first and second die and interposer. A portion of the interposer can be removed to that the encapsulant forms around a side of the semiconductor device. An interconnect structure is formed over the interposer and second die.
    Type: Grant
    Filed: February 26, 2010
    Date of Patent: January 23, 2018
    Assignee: STATS ChipPAC Pte. Ltd.
    Inventors: Reza A. Pagaila, Yaojian Lin, Jun Mo Koo, HeeJo Chi
  • Patent number: 9876036
    Abstract: The present invention provides a TFT arrangement structure, comprising a first thin film transistor (T1) and a second thin film transistor (T2) controlled by the same control signal line; the first active layer (SC1) of the first thin film transistor (T1) and the second active layer (SC2) of the second thin film transistor (T2) are at different layers, and positioned to stack up in space, and the first source (S1) and the first drain (D1) of the first thin film transistor (T1) are formed on the first active layer (SC1), and the second source (S2) and the second drain (D2) of the second thin film transistor (T2) are formed on the second active layer (SC2); the gate layer (Gate) is electrically coupled to the control signal line to control on and off of the first, the second thin film transistors (T1, T2).
    Type: Grant
    Filed: May 21, 2015
    Date of Patent: January 23, 2018
    Assignee: SHENZHEN CHINA STAR OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventors: Baixiang Han, Longqiang Shi
  • Patent number: 9871166
    Abstract: The light emitting device 1 includes a substrate 2, and an n-type conductive type semiconductor layer 3, a light emitting layer 4 and a p-type conductive type semiconductor layer 5 laminated in series on a surface 2A of the substrate 2. The light emitting layer 4, the p-type conductive type semiconductor layer 5, and a portion of the n-type conductive type semiconductor layer 3 excluding the vicinity of the peripheral portion compose a semiconductor laminate structure portion 6. A p-side transparent electrode layer 14 is formed on a surface of the p-type conductive type semiconductor layer 5. The p-side transparent electrode 14 covers a substantially whole area of a predetermined current injection region 13 on a surface of the p-type conductive type semiconductor layer 5. A p-side electrode 15 is formed on a surface of the p-side transparent electrode layer 14.
    Type: Grant
    Filed: January 20, 2015
    Date of Patent: January 16, 2018
    Assignee: ROHM CO., LTD.
    Inventors: Takao Fujimori, Tomohito Kawase, Yasuo Nakanishi
  • Patent number: 9859270
    Abstract: An ESD protection device includes an MOS transistor with a source region, drain region and gate region. A node designated for ESD protection is electrically coupled to the drain. A diode is coupled between the gate and source, wherein the diode would be reverse biased if the MOS transistor were in the active operating region.
    Type: Grant
    Filed: August 20, 2015
    Date of Patent: January 2, 2018
    Assignee: Infineon Technologies AG
    Inventors: Cornelius Christian Russ, David Alvarez
  • Patent number: 9853161
    Abstract: A thin film transistor (TFT) is provided which is capable of reducing leakage currents in a polycrystalline silicon TFT without causing an increase in manufacturing processes. Source/drain regions of an activated layer of the TFT to be formed in a circuit region and pixel region formed on a glass substrate of a liquid crystal display panel for a mobile phone is formed so that its boron impurity falls within a range of 2.5×1018/cm3 to 5.5×1018/cm3 and its impurity activation falls within a range of 1% to 7%.
    Type: Grant
    Filed: March 19, 2010
    Date of Patent: December 26, 2017
    Assignee: NLT TECHNOLOGIES, LTD.
    Inventor: Kunihiro Shiota
  • Patent number: 9842797
    Abstract: A stacked die power converter package includes a lead frame including a die pad and a plurality of package pins, a first die including a first power transistor switch (first power transistor) attached to the die pad, and a first metal clip attached to one side of the first die. The first metal clip is coupled to at least one package pin. A second die including a second power transistor switch (second power transistor) is attached to another side on the first metal clip. A controller is provided by a controller die attached to a non-conductive layer on the second metal clip on one side of the second die.
    Type: Grant
    Filed: November 4, 2013
    Date of Patent: December 12, 2017
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Brian A. Carpenter, Christopher Sanzo, William T. Harrison, Alok Lohia, Matthew D. Romig
  • Patent number: 9831164
    Abstract: A semiconductor device includes a via structure and a conductive structure. The via structure has a surface with a planar portion and a protrusion portion. The conductive structure is formed over at least part of the planar portion and not over at least part of the protrusion portion of the via structure. For example, the conductive structure is formed only onto the planar portion and not onto any of the protrusion portion for forming high quality connection between the conductive structure and the via structure.
    Type: Grant
    Filed: February 1, 2013
    Date of Patent: November 28, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Kwang-jin Moon, Pil-kyu Kang, Dae-lok Bae, Gil-heyun Choi, Byung-lyul Park, Dong-chan Lim, Deok-young Jung
  • Patent number: 9831255
    Abstract: A semiconductor device includes a lower electrode, a ferroelectric film on the lower electrode, an upper electrode on the ferroelectric film, and a first insulating film covering a surface and a side of the upper electrode, a side of the ferroelectric film, and a side of the lower electrode. The first insulating film includes a first opening that exposes a portion of the surface of the upper electrode. A second insulating film covers the first insulating film and includes a second opening that exposes the portion of the surface of the upper electrode through a second opening. A barrier metal is formed in the first opening and the second opening, and is connected to the upper electrode. A connection region in which a material of the barrier metal interacts with a material of the upper electrode extends below an upper-most surface of the upper electrode.
    Type: Grant
    Filed: July 28, 2016
    Date of Patent: November 28, 2017
    Assignee: ROHM CO., LTD.
    Inventor: Yuichi Nakao
  • Patent number: 9831341
    Abstract: The present disclosure provides many different embodiments of an IC device. The IC device includes a gate stack disposed over a surface of a substrate and a spacer disposed along a sidewall of the gate stack. The spacer has a tapered edge that faces the surface of the substrate while tapering toward the gate stack. Therefore the tapered edge has an angle with respect to the surface of the substrate.
    Type: Grant
    Filed: June 16, 2014
    Date of Patent: November 28, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Shin-Jiun Kuang, Tsung-Hsing Yu, Yi-Ming Sheu
  • Patent number: 9825096
    Abstract: According to one embodiment, a resistance change memory includes a first conductive line, a second conductive line provided above the first conductive line, and extending in a first direction, a third conductive line extending in a second direction intersecting the first direction, a select transistor provided between the first and third conductive lines, and a resistance change layer provided between the second and third conductive lines.
    Type: Grant
    Filed: June 23, 2015
    Date of Patent: November 21, 2017
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Kensuke Ota, Masumi Saitoh
  • Patent number: 9818918
    Abstract: An LED package structure includes a carrier mounted with a plurality of LED chips, a first glue-layer, a second glue-layer and an encapsulation resin filled within the first and the second glue-layers. The first glue-layer is formed on a top surface of the carrier and has a thin-film structure which is substantially flat on a top surface thereof. The second glue-layer is stacked on the first glue-layer. The second glue-layer has a height higher than that of the first glue-layer. The second glue-layer has a volume greater than that of the first glue-layer. The present invention also provides a method of LED package structure to stably produce a dam structure with uniform shape and high ratio of height/width.
    Type: Grant
    Filed: December 20, 2013
    Date of Patent: November 14, 2017
    Assignees: LITE-ON ELECTRONICS (GUANGZHOU) LIMITED, LITE-ON TECHNOLOGY CORPORATION
    Inventor: Kuo-Ming Chiu
  • Patent number: 9818875
    Abstract: A method of fabricating a vertical fin field effect transistor with a strained channel, including, forming a strained vertical fin on a substrate, forming a plurality of gate structures on the strained vertical fin, forming an interlevel dielectric on the strained vertical fin, forming a source/drain contact on the vertical fin adjacent to each of the plurality of gate structures, and selectively removing one or more of the source/drain contacts to form a trench adjacent to a gate structure.
    Type: Grant
    Filed: October 17, 2016
    Date of Patent: November 14, 2017
    Assignee: International Business Machines Corporation
    Inventors: Zhenxing Bi, Kangguo Cheng, Juntao Li, Peng Xu
  • Patent number: 9806273
    Abstract: A field effect transistor array comprising a substrate and a plurality of single wall carbon nano-tubes disposed on a surface of the substrate. A plurality of electrodes are disposed over the nano-tubes such that the conductive strips are spaced-apart from each other. These electrodes form the contact point for the drain and source of the field effect transistor, while one or more of the nano-carbon tubes form the channel between the source and the drain.
    Type: Grant
    Filed: April 23, 2007
    Date of Patent: October 31, 2017
    Assignee: The United States of America as represented by the Secretary of the Army
    Inventors: Shashi P. Karna, Govind Mallick
  • Patent number: 9806158
    Abstract: The present disclosure relates to a high electron mobility transistor compatible power lateral field-effect rectifier device. In some embodiments, the rectifier device has an electron supply layer located over a layer of semiconductor material at a position between an anode terminal and a cathode terminal. A layer of doped III-N semiconductor material is disposed over the electron supply layer. A layer of gate isolation material is located over the layer of doped III-N semiconductor material. A gate structure is disposed over layer of gate isolation material, such that the gate structure is separated from the electron supply layer by the layer of gate isolation material and the layer of doped III-N semiconductor material. The layer of doped III-N semiconductor material modulates the threshold voltage of the rectifier device, while the layer of gate isolation material provides a barrier that gives the rectifier device a low leakage.
    Type: Grant
    Filed: August 1, 2013
    Date of Patent: October 31, 2017
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: King-Yuen Wong, Yu-Syuan Lin, Chih-Wen Hsiung
  • Patent number: 9806106
    Abstract: The present invention provides a thin film transistor array substrate and a manufacture method thereof, comprising: a substrate (1) and a thin film transistor and a storage capacitor formed on the substrate (1); the storage capacitor comprises a first electrode plate (31) on the substrate (1), a gate isolation layer (31) or an etching stopper layer (5) on the first electrode plate (31), a second electrode plate (32) on the gate isolation layer (3) or the etching stopper layer (5); there is only one isolation layer, which is the gate isolation layer or the etching stopper layer, existing between the two electrode plates of the storage capacitor in the aforesaid thin film transistor array substrate, the isolation layer thickness of the storage capacitor is thinner, and relatively, the capacitor occupies a smaller area and possesses a higher aperture ratio.
    Type: Grant
    Filed: May 21, 2015
    Date of Patent: October 31, 2017
    Assignee: SHENZHEN CHINA STAR OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventor: Xiaowen Lv
  • Patent number: 9799679
    Abstract: The present disclosure provides a thin film transistor (TFT) array substrate, its manufacturing method and a display device. The method includes steps of: forming patterns of a common electrode, a common electrode line, a gate line and a data line on a substrate by a single patterning process; forming an insulating layer; forming a pattern of an active layer by a single patterning process; forming a gate insulating layer and forming via-holes corresponding to the gate line, the data line and the active layer in the gate insulating layer by a single patterning process; and forming patterns of a pixel electrode, a gate electrode, a source electrode and a drain electrode by a single patterning process.
    Type: Grant
    Filed: October 31, 2014
    Date of Patent: October 24, 2017
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventor: Ce Ning
  • Patent number: 9793376
    Abstract: In a method of manufacturing a silicon carbide semiconductor device including a vertical switching element having a trench gate structure, with the use of a substrate having an off angle with respect to a (0001) plane or a (000-1) plane, a trench is formed from a surface of a source region to a depth reaching a drift layer through a base region so that a side wall surface of the trench faces a (11-20) plane or a (1-100) plane, and a gate oxide film is formed without performing sacrificial oxidation after formation of the trench.
    Type: Grant
    Filed: August 6, 2013
    Date of Patent: October 17, 2017
    Assignees: DENSO CORPORATION, TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: Shinichiro Miyahara, Toshimasa Yamamoto, Jun Morimoto, Narumasa Soejima, Yukihiko Watanabe
  • Patent number: 9786553
    Abstract: A semiconductor structure including a back-end-of-the-line (BEOL) interconnect structure that contains an air gap located on each side of an interconnect metal or metal alloy structure, is provided wherein each air gap has a uniform (i.e., homogenous) shape. The uniform shape of the air gap can aide in reducing the electrical performance variation which is typically observed with prior art interconnect structures containing air gaps that have a non-uniform shape.
    Type: Grant
    Filed: September 16, 2016
    Date of Patent: October 10, 2017
    Assignee: International Business Machines Corporation
    Inventor: Chih-Chao Yang