Patents Examined by Ori Nadav
  • Patent number: 10133139
    Abstract: A structure for preventing deteriorations of a light-emitting device and retaining sufficient capacitor elements (condenser) required by each pixel is provided. A first passivation film, a second metal layer, a flattening film, a barrier film, and a third metal layer are stacked in this order over a transistor. A side face of a first opening provided with the flattening film is covered by the barrier film, a second opening is formed inside the first opening, and a third metal layer is connected to a semiconductor via the first opening and the second opening. A capacitor element that is formed of a lamination of a semiconductor of a transistor, a gate insulating film, a gate electrode, the first passivation film, and the second metal layer is provided.
    Type: Grant
    Filed: October 10, 2014
    Date of Patent: November 20, 2018
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Toru Takayama, Satoshi Murakami, Hajime Kimura
  • Patent number: 10109718
    Abstract: A semiconductor component and a method for manufacturing the semiconductor component, wherein the semiconductor component includes a transient voltage suppression structure that includes at least two diodes and a Zener diode. In accordance with embodiments, a semiconductor material is provided that includes an epitaxial layer. The at least two diodes and the Zener diode are created at the surface of the epitaxial layer, where the at least two diodes may be adjacent to the Zener diode.
    Type: Grant
    Filed: May 1, 2014
    Date of Patent: October 23, 2018
    Assignee: Semiconductor Components Industries, LLC
    Inventors: Umesh Sharma, Harry Yue Gee, Der Min Liou, David D Marreiro, Sudhama C Shastri
  • Patent number: 10104480
    Abstract: Synthetically generated signals are reproduced via a binaural hearing system, which includes two hearing devices. After reproducing a first signal via the first hearing device a reproduction of a second signal via the second hearing device is also carried out delayed by a defined time interval. The additional time delay is to be quantified such that the impression of a sound amplification is produced with a hearing system wearer.
    Type: Grant
    Filed: March 25, 2008
    Date of Patent: October 16, 2018
    Assignee: Sivantos GmbH
    Inventors: Ulrich Kornagel, Wolfgang Sörgel
  • Patent number: 10081538
    Abstract: The present invention discloses a Micro-Electro-Mechanical System (MEMS) acoustic pressure sensor device and a method for making same. The MEMS device includes: a substrate; a fixed electrode provided on the substrate; and a multilayer structure, which includes multiple metal layers and multiple metal plugs, wherein the multiple metal layers are connected by the multiple metal plugs. A cavity is formed between the multilayer structure and the fixed electrode. Each metal layer in the multilayer structure includes multiple metal sections. The multiple metal sections of one metal layer and those of at least another metal layer are staggered to form a substantially blanket surface as viewed from a moving direction of an acoustic wave.
    Type: Grant
    Filed: April 23, 2017
    Date of Patent: September 25, 2018
    Inventor: Chuan-Wei Wang
  • Patent number: 10079324
    Abstract: A semiconductor light-receiving device includes: a semi-insulating substrate; and a buffer layer, a p-type contact layer, a light absorption layer, a p-type field alleviating layer, an avalanche multiplication layer, an n-type field alleviating layer and an n-type contact layer laminated in order on the semi-insulating substrate, wherein the buffer layer includes a superlattice obtained by alternately laminating an InP layer and an AlxGayIn1-x-yAs layer (0.16?x?0.48, 0?y?0.31) and does not absorb light of a wavelength band absorbed by the light absorption layer.
    Type: Grant
    Filed: February 26, 2016
    Date of Patent: September 18, 2018
    Assignee: Mitsubishi Electric Corporation
    Inventor: Harunaka Yamaguchi
  • Patent number: 10074646
    Abstract: A protective circuit includes a non-linear element, which further includes a gate electrode, a gate insulating layer covering the gate electrode, a pair of first and second wiring layers whose end portions overlap with the gate electrode over the gate insulating layer and in which a conductive layer and a second oxide semiconductor layer are stacked, and a first oxide semiconductor layer which overlaps with at least the gate electrode and which is in contact with side face portions of the gate insulating layer and the conductive layer of the first wiring layer and the second wiring layer and a side face portion and a top face portion of the second oxide semiconductor layer. Over the gate insulating layer, oxide semiconductor layers with different properties are bonded to each other, whereby stable operation can be performed as compared with Schottky junction. Thus, the junction leakage can be decreased and the characteristics of the non-linear element can be improved.
    Type: Grant
    Filed: May 10, 2016
    Date of Patent: September 11, 2018
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Kengo Akimoto, Shigeki Komori, Hideki Uochi, Tomoya Futamura, Takahiro Kasahara
  • Patent number: 10062778
    Abstract: A semiconductor device according to the present invention includes: an insulating layer; a semiconductor layer of a first conductive type laminated on the insulating layer; an annular deep trench having a thickness reaching the insulating layer from a top surface of the semiconductor layer; a body region of a second conductive type formed across an entire thickness of the semiconductor layer along a side surface of the deep trench in an element forming region surrounded by the deep trench; a drift region of the first conductive type constituted of a remainder region besides the body region in the element forming region; a source region of the first conductive type formed in a top layer portion of the body region; a drain region of the first conductive type formed in a top layer portion of the drift region; and a first conductive type region formed in the drift region, having a deepest portion reaching a position deeper than the drain region, and having a first conductive type impurity concentration higher tha
    Type: Grant
    Filed: March 7, 2016
    Date of Patent: August 28, 2018
    Assignee: ROHM CO., LTD.
    Inventors: Naoki Izumi, Tomoyasu Sada
  • Patent number: 10050233
    Abstract: An organic light emitting diode includes an anodic conductive layer, an organic EL layer, and a cathodic conductive layer formed from Ag or an alloy of Ag, or the like, sequentially laminated on a substrate, such that a two-dimensional lattice structure is provided on a surface of the cathodic conductive layer on an organic EL layer side, an extraction wavelength and a distance between centers of concave portions or convex portions in the two-dimensional lattice structure are within a region surrounded by specific coordinates in a graph illustrating a relationship between the light extraction wavelength and the distance, and the depth of the concave portions or a height of the convex portions is 12 nm to 180 nm.
    Type: Grant
    Filed: June 28, 2017
    Date of Patent: August 14, 2018
    Assignee: OJI Holdings Corporation
    Inventors: Kei Shinotsuka, Takayuki Okamoto
  • Patent number: 10043893
    Abstract: Methods of forming a graded SiGe percentage PFET channel in a FinFET or FDSOI device by post gate thermal condensation and oxidation of a high Ge percentage channel layer and the resulting devices are provided. Embodiments include forming a gate dielectric layer over a plurality of Si fins formed over a substrate; forming a gate over each fin; forming a HM and spacer layer over and on sidewalls of each gate; forming a u-shaped cavity in each fin adjacent to the gate and spacer layer; epitaxially growing an un-doped high percentage SiGe layer in each u-shaped cavity and along sidewalls of each fin; thermally condensing the high percentage SiGe layer, an un-doped low percentage SiGe formed underneath in the substrate and fins; and forming a S/D region over the high percentage SiGe layer in each u-shaped cavity, an upper surface of the S/D regions below the gate dielectric layer.
    Type: Grant
    Filed: August 3, 2017
    Date of Patent: August 7, 2018
    Inventors: George Robert Mulfinger, Ryan Sporer, Timothy J. McArdle, Judson Robert Holt
  • Patent number: 10002896
    Abstract: Infrared radiation micro device, cover for such a device and method for its fabrication, the device comprising a substrate and a cover and an infrared radiation detecting, emitting or reflecting infrared micro unit, the infrared micro unit being arranged in a cavity defined between the substrate and the cover, the cover comprising an antireflective surface texture to enhance the transmissibility of infrared radiation, wherein a distance frame formed in an additive process on the substrate side of the cover and/or the cover side of the substrate is arranged between substrate and cover.
    Type: Grant
    Filed: June 21, 2010
    Date of Patent: June 19, 2018
    Inventors: Wolfgang Reinert, Jochen Quenzer, Sebastien Tinnes, Cécile Roman
  • Patent number: 9997411
    Abstract: Embodiments of present disclosure provide methods of forming a resistor. One such method can include forming a first transistor structure and a second transistor structure on a semiconductor substrate, wherein the first transistor structure includes a dummy gate thereon; forming a mask on the first transistor structure; forming a metal gate on the second transistor structure; removing the mask, after the forming of the metal gate, to expose the first transistor structure; and siliciding a top portion of the dummy gate of the first transistor structure to yield a resistor.
    Type: Grant
    Filed: August 27, 2015
    Date of Patent: June 12, 2018
    Assignee: International Business Machines Corporation
    Inventors: Cung Tran, Emre Alptekin, Viraj Sardesai, Reinaldo Vega
  • Patent number: 9985038
    Abstract: Prior known static random access memory (SRAM) cells are required that a diffusion layer be bent into a key-like shape in order to make electrical contact with a substrate with a P-type well region formed therein, which would result in a decrease in asymmetry leading to occurrence of a problem as to the difficulty in micro-patterning. To avoid this problem, the P-type well region in which an inverter making up an SRAM cell is formed is subdivided into two portions, which are disposed on the opposite sides of an N-type well region NW1 and are formed so that a diffusion layer forming a transistor has no curvature while causing the layout direction to run in a direction parallel to well boundary lines and bit lines. At intermediate locations of an array, regions for use in supplying power to the substrate are formed in parallel to word lines in such a manner that one regions is provided per group of thirty two memory cell rows or sixty four cell rows.
    Type: Grant
    Filed: March 2, 2017
    Date of Patent: May 29, 2018
    Assignee: Renesas Electronics Corporation
    Inventors: Kenichi Osada, Masataka Minami, Shuji Ikeda, Koichiro Ishibashi
  • Patent number: 9978776
    Abstract: A pixel portion and a driver circuit driving the pixel portion are formed over the same substrate. At least a part of the driver circuit is formed using an inverted staggered thin film transistor in which an oxide semiconductor layer is used and a channel protective layer is provided over the oxide semiconductor layer serving as a channel formation region which is overlapped with the gate electrode. The driver circuit as well as the pixel portion is provided over the same substrate to reduce manufacturing costs.
    Type: Grant
    Filed: April 5, 2016
    Date of Patent: May 22, 2018
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Kengo Akimoto, Atsushi Umezaki
  • Patent number: 9978844
    Abstract: The present disclosure relates to a high electron mobility transistor compatible power lateral field-effect rectifier (L-FER) device. In some embodiments, the rectifier device has an electron supply layer located over a layer of semiconductor material at a position between an anode terminal and a cathode terminal. A layer of doped III-N semiconductor material is disposed over the electron supply layer. A passivation layer is located over the electron supply layer and the layer of doped III-N semiconductor material. A gate structure is disposed over the layer of doped III-N semiconductor material and the passivation layer. The layer of doped III-N semiconductor material modulates the threshold voltage of the rectifier device, while the passivation layer improves reliability of the L-FER device by mitigating current degradation due to high-temperature reverse bias (HTRB) stress.
    Type: Grant
    Filed: December 26, 2014
    Date of Patent: May 22, 2018
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: King-Yuen Wong, Ming-Wei Tsai, Han-Chin Chiu
  • Patent number: 9955268
    Abstract: A micro-electrical-mechanical system (MEMS) microphone includes a MEMS structure, having a substrate, a diaphragm, and a backplate, wherein the substrate has a cavity and the backplate is between the cavity and the diaphragm. The backplate has multiple venting holes, which are connected to the cavity and allows the cavity to extend to the diaphragm. Further, an adhesive layer is disposed on the substrate, surrounding the cavity. A cover plate is adhered on the adhesive layer, wherein the cover plate has an acoustic hole, dislocated from the cavity without direct connection.
    Type: Grant
    Filed: July 11, 2014
    Date of Patent: April 24, 2018
    Assignee: Solid State System Co., Ltd.
    Inventors: Tsung-Min Hsieh, Chien-Hsing Lee, Cheng-Wei Tsai, Jhyy-Cheng Liou
  • Patent number: 9947771
    Abstract: A method of fabricating a thin film transistor includes forming a substrate having first and second regions, a semiconductor layer pattern formed in the first region and the second region, and a first gate insulating layer pattern formed on a channel region of the semiconductor layer pattern of the first region. A second gate insulating layer is formed on the substrate, a first conductive layer pattern is formed above the channel region of the first region and above the semiconductor layer pattern of the second region, and an inter-layer insulating layer is formed on the substrate. A second conductive layer pattern is formed in the first region and above the first conductive layer pattern of the second region. The second conductive layer pattern of the first region is coupled to the semiconductor layer pattern of the first region through the second gate insulating layer and the inter-layer insulating layer.
    Type: Grant
    Filed: June 3, 2015
    Date of Patent: April 17, 2018
    Assignee: Samsung Display Co., Ltd.
    Inventor: Byoung-Keon Park
  • Patent number: 9929007
    Abstract: The present disclosure relates to a structure and method for reducing dangling bonds around quantum dots in a memory cell. In some embodiments, the structure has a semiconductor substrate having a tunnel dielectric layer disposed over it and a plurality of quantum dots disposed over the tunnel dielectric layer. A passivation layer is formed conformally over outer surfaces of the quantum dots and a top dielectric layer is disposed conformally around the passivation layer. The passivation layer can be formed prior to forming the top dielectric layer over the quantum dots or after forming the top dielectric layer. The passivation layer reduces the dangling bonds at an interface between the quantum dots and the top dielectric layer, thereby preventing trap sites that may hinder operations of the memory cell.
    Type: Grant
    Filed: December 26, 2014
    Date of Patent: March 27, 2018
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chih-Ming Chen, Tsu-Hui Su, Szu-Yu Wang, Chung-Yi Yu, Chia-Shiung Tsai
  • Patent number: 9911750
    Abstract: Semiconductor memory devices may include a semiconductor substrate, a first stack disposed on the semiconductor substrate and a second stack disposed on the first stack. The first stack may include a plurality of first word lines with a plurality of first line pads stacked in a stair form, and the second stack may include a plurality of second word lines with a plurality of second line pads stacked in a stair form. The second stack may be shifted on the first stack such that sides of the plurality of first word line pads are exposed.
    Type: Grant
    Filed: January 15, 2016
    Date of Patent: March 6, 2018
    Inventor: Jaegoo Lee
  • Patent number: 9893071
    Abstract: A semiconductor device and a method for forming the same are disclosed. The semiconductor device includes a semiconductor substrate including an active region defined by a device isolation film, a bit line contact plug that is coupled to the active region and that includes a first ion implantation region buried in a first inner void, and a storage node contact plug that is coupled to the active region and includes a second ion implantation region buried in a second inner void. Although the semiconductor device is highly integrated, a contact plug is buried to prevent formation of a void, so that increase in contact plug resistance is prevented, resulting in improved semiconductor device characteristics.
    Type: Grant
    Filed: February 22, 2016
    Date of Patent: February 13, 2018
    Assignee: SK HYNIX INC.
    Inventors: Jae Soo Kim, Jae Chun Cha
  • Patent number: 9876037
    Abstract: The present invention provides a thin-film transistor array substrate and a manufacturing method thereof. In the thin-film transistor array substrate of the present invention, the portion of the gate insulation layer interposed between two electrode plates of the storage capacitor is smaller than that of the remaining portion of the gate insulation layer so that the thickness of the insulation layer of the storage capacitor is reduced and the area of the opposite surfaces of the capacitor can be made smaller and an increased aperture ratio can be achieved.
    Type: Grant
    Filed: May 25, 2015
    Date of Patent: January 23, 2018
    Inventors: Xiaowen Lv, Chihyu Su