Abstract: A method (and corresponding system, computer program and storage device) for testing a device under test, DUT, comprising: generating or receiving, by a component of the DUT, a bus signal, wherein the bus signal comprises a first data signal having a plurality of first phase angles or a second data signal having a plurality of second phase angles; averaging the phase angles for a predetermined bus signal length; comparing the averaged phase angle with a preset phase range; and identifying the first data signal or the second data signal in the bus signal based on the comparison.

Abstract: A communication system and an operation method thereof are provided. A transmitting device transmits a data unit to a receiving device through a data channel of a communication interface. The transmitting device calculates an original verification information unit of the data unit and synchronously transmits the original verification information unit to the receiving device through a verification information channel of the communication interface based on a transmission timing of the data unit in the data channel. After receiving a current data unit and before receiving a next data unit, the receiving device verifies whether the current data unit received from the data channel has errors in real time based on a current original verification information unit corresponding to the current data unit.

Abstract: The present disclosure relates to a quantum error correction code and, more particularly, to a method and apparatus for optimizing a quantum error correction code in biased error environment. The method for optimizing a quantum error correction code, according to an embodiment of the present disclosure, may comprise the steps of: estimating, on the basis of a physical error rate (pphy) and a bias degree (?), a logical error rate (Pfail) for each of one or more candidate lattice sizes; determining, on the basis of the estimated logical error rate (Pfail) and a target logical error rate (Pf,target), an optimal lattice size from among the one or more candidate lattice sizes; and arranging a Qubit on the basis of the optimal lattice size. Here, when the bias degree (?) exceeds 1, the one or more candidate lattice sizes may be defined in the form of a rectangular excluding a square.

Abstract: A method can include obtaining, at a physical communication layer integrated with a communication interface, a data packet, detecting, by a detection circuit integrated with the physical communication layer, a portion of data in the data packet corresponding to a marker identifying the data packet, linking, by the physical communication layer based on the marker, a timestamp with the data packet, and transmitting, by the physical communication layer, the data packet linked with the timestamp.

Abstract: A processing device in a memory sub-system identifies a set of parameters associated with one or more errors detected with respect to a memory device of a memory sub-system. A vector representing the set of parameters is generated. Based on the vector, a classification value corresponding to the one or more errors is generated. Based on the classification value, a set of error recovery operations is selected from a plurality of sets of error recovery operations, and the set of error recovery operations is executed.

Abstract: Various aspects of the present disclosure generally relate to wireless communication. In some aspects, a user equipment (UE) may receive an indication associated with Type B physical uplink channel repetitions of a transport block. The UE may transmit the repetitions of the transport block, including a first smaller repetition of the repetitions that has a first payload size that is smaller than a nominal payload size for the repetitions and that includes a first self-decodable data portion of the transport block. Numerous other aspects are described.

Abstract: Provided is an information processing device which includes a processing unit that transmits information requesting retransmission in a coding unit of a first code processed in a second protocol layer higher than a first protocol layer that performs processing related to a second code, and performs decoding of the first code on a basis of an encoded symbol of the first code obtained by decoding of the second code.

Abstract: Systems, methods, apparatuses, and computer program products for hierarchical coding. One method may include encoding, by a layer-0 autoencoder, bit sequence x into a layer-0 codeword. The method may further include transmitting, by the layer-0 autoencoder, the layer-0 codeword over a channel, and decoding, by the layer-0 decoder, a received layer-0 codeword.

Abstract: An electronic device is provided, which includes an oscillator, a controller, and a test circuit. The oscillator generates a clock signal according to an enable signal. The oscillator determines a period of the clock signal according to an adjustment signal. The controller generates the enable signal and generates a first test signal according to the clock signal. The controller determines the period according to a first comparison signal and a second comparison signal. The test circuit, through the first test signal, tests the period to generate the first comparison signal and the second comparison signal.

Abstract: Methods, systems, and devices for wireless communication are described. A wireless device may transmit feedback, such as hybrid automatic repeat request (HARQ) feedback for groups of code blocks rather than for an entire transport block or individual code blocks. The wireless device may transmit an acknowledgement (ACK) or negative-acknowledgement (NACK) to provide feedback for each code block group of a set of code block groups. An ACK may indicate that code blocks in a code block group were successfully decoded, and a NACK may indicate that at least one code block in a code block group was not successfully decoded. Wireless devices may support several techniques for grouping code blocks for feedback reporting to allow for efficient retransmissions and limited overhead. Different grouping schemes may be employed depending on system constraints, device capability, link conditions, or the like.

Abstract: An encoding method and apparatus, a decoding method and apparatus, and a device are provided. The encoding method includes obtaining K to-be-encoded bits (S301), where K is a positive integer; determining a first generator matrix, where the first generator matrix includes at least two sub-blocks distributed based on a preset position relationship, and the sub-block includes a plurality of first generator matrix cores (S302); generating a second generator matrix based on the first generator matrix, where the second generator matrix includes T sub-blocks, and a position relationship between two adjacent sub-blocks of the T sub-blocks is determined based on the preset position relationship (S303), where T is a positive integer; and polar encoding the K to-be-encoded bits based on the second generator matrix (S304), to obtain encoded bits. This reduces encoding/decoding complexity.

Abstract: Methods and apparatus are described herein for improved efficiency of a wireless transmit/receive unit (WTRU) transmitting transport blocks (TBs). A WTRU may receive configuration information including uplink resources associated with one or more repetition bundles and a target number of retransmissions for a transport block (TB) associated with at least one hybrid automatic repeat request (HARQ) process. Then, the WTRU may transmit a first TB using a first uplink resource in a first repetition bundle based on the configuration information. Further, the WTRU may increment a retransmission counter. On a condition that the retransmission counter is less than the target number of retransmissions, the WTRU may determine a second uplink resource. Further, the WTRU may retransmit the first TB in the determined second uplink resource. Also, the WTRU may further increment the retransmission counter. Moreover, the first, second and third uplink resources may be physical uplink shared channel (PUSCH) resources.

Abstract: A method for accelerating bit error correction in a receiver in a radio communication network, wherein the receiver is configured to update soft bit values associated with each code bit of a block code based on parallel parity checks. The method includes receiving a block code encoded message, and for any group of two or more rows of a parity-check matrix of the block code: when the two or more rows are non-overlapping: combining the two or more rows in a row group for parallel updating, updating, in parallel, the parity checks of the row group for the received message, and forming a message estimate based on the updated parity checks. Corresponding computer program product, apparatus, and receiver are also disclosed.

Abstract: Methods and apparatuses for improving telecommunications services by intelligently deploying radio access network components and redundant links within a data center hierarchy to satisfy latency, power, availability, and quality of service requirements for one or more network slices are described. The radio access network components may include virtualized distributed units (VDUs) and virtualized centralized units (VCUs). To satisfy a latency requirement for a network slice, various components of a radio access network may need to be redeployed closer to user equipment. To satisfy a power requirement for the network slice, various components of the radio access network may need to be redeployed closer to core network components. Over time, the components of the radio access network may be dynamically reassigned to different layers within a data center hierarchy in order to satisfy changing latency requirements and power requirements for the network slice.

Abstract: The invention relates to an apparatus and a method for generating a Low-Density Parity-Check (LDPC) code. The apparatus includes: a LDPC encoder, a look-ahead circuitry and an exclusive-OR (XOR) calculation circuitry. The LDPC encoder is arranged operably to encode a front part of a user data using a 2-stage encoding algorithm with a parity check matrix to generate a first calculation result. The look-ahead circuitry is arranged operably to perform a dot product operation on a rear part of the user data and one of a plurality of feature rows corresponding to the parity check matrix to generate a second calculation result in each iteration. The XOR calculation circuitry is arranged operably to perform an XOR operation on the first calculation result and the second calculation result to generate a front part of the LDPC code.

Abstract: In an embodiment, an error correction code circuit is provided. The error correction code circuit includes an error correction code engine and data processing circuit. The error correction code engine is configured to generate a second parity signal and syndrome information by performing an operation on operation source data and a first parity signal. The data processing circuit is configured to output write data as the operation source data and output an internally generated dummy parity signal as the first parity signal during a write operation, and to output read data as the operation source data and output a read parity signal as the first parity signal during a read operation.

Abstract: Systems and methods to transmit data over multiple communication channels in parallel with forward error correction. Original packets are evenly distributed to the channels as the initial systematically channel-encoded packets. Subsequent channel-encoded packets are configured to be linearly independent of their base sets of channel-encoded packets, where a base set for a subsequent channel-encoded packet includes those scheduled to be transmitted before the subsequent packet in the same channel as the subsequent packet, and optionally one or more initial packets from other channels. The compositions of the sequences of the encoded packets can be predetermined without the content of the packets; and the channel-encoded packets can be generated from the original packets on-the-fly by the transmitters of the channels during transmission. When a sufficient number of packets have been received via the channels, a recipient may terminate their transmissions.

Abstract: A method including determining that a memory unit is available for a channel for communication between a storage controller and a non-volatile storage device, the memory unit being for temporary storage for encoded data for transmission through the channel; allocating the memory unit to that channel; and updating a memory mapping entry corresponding to the memory unit. The memory mapping entry is stored in the storage controller. Updating a memory mapping entry may be based on reading/write tasks. The memory mapping entry may indicate a cross channel status, an operation mode and an identifier of the channel. The method may include determining the channel being stuck due to memory shortage and mapping more memory units to the channel.

Abstract: An apparatus is described. The apparatus includes a memory controller having logic circuitry to write a unit of write data into a plurality of memory chips according to a striping pattern that includes multiple protected sub words, each protected sub word including a smaller portion of the unit of write data and error correction coding (ECC) information calculated from the smaller portion of the unit of write data.

Abstract: The present disclosure relates to an apparatus (100) for joint test action group (JTAG) and scan emulation, the apparatus includes a controller circuitry (102) that is interfaced to a target integrated circuit (IC) (106) for testing the target IC, the controller circuitry having one or more serial peripheral interface (SPI) devices (104-1, 104-2) operating in master mode and slave mode. The controller circuitry (102) operates the one or more SPI devices (104-1, 104-2) to switch between a first mode and a second mode dynamically to emulate JTAG and scan test functionality. The controller circuitry facilitates reusing the one or more SPI devices located in the controller circuitry to emulate JTAG and scan test interface protocols without any additional hardware requirements.