Patents Examined by Pablo Huerta
  • Patent number: 9293198
    Abstract: A method for programming gated phase-change memory cells, each with a gate, source and drain, having s?2 programmable cell-states including an amorphous RESET state and at least one crystalline state includes applying a programming signal between the source and drain of a memory cell to program that cell to a desired cell-state; and when programming the cell from a crystalline state to the RESET state, applying a bias voltage to the gate of the cell to increase the cell resistance.
    Type: Grant
    Filed: May 22, 2013
    Date of Patent: March 22, 2016
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventor: Daniel Krebs
  • Patent number: 9286954
    Abstract: A buffer circuit of a semiconductor apparatus includes a sensing circuit configured to sense input signals according to a data strobe signal, generate latch control signals, provide the latch control signals at nodes, and remove parasitic components of the nodes in response to a clock signal; and a latch circuit configured to generate and latch output data in response to the latch control signals.
    Type: Grant
    Filed: February 28, 2014
    Date of Patent: March 15, 2016
    Assignee: SK Hynix Inc.
    Inventor: Jin Ha Hwang
  • Patent number: 9287855
    Abstract: A semiconductor device includes a pipe latch suitable for sequentially latching data in response to a pipe input control signal and sequentially outputting data in response to a pipe output control signal, a pipe latch control unit suitable for generating the pipe input/output control signals in response to a command signal and latency information, and resetting the pipe input/output control signals in response to a pipe reset signal, and an error detection unit suitable for receiving the pipe input control signal and the pipe output control signal, detecting a latency error, and generating the pipe reset signal.
    Type: Grant
    Filed: December 15, 2013
    Date of Patent: March 15, 2016
    Assignee: SK Hynix Inc.
    Inventor: Kie-Bong Ku
  • Patent number: 9286979
    Abstract: The present disclosure provides a resistive random access memory (RRAM) structure. The RRAM structure includes a bottom electrode on a substrate; a resistive material layer on the bottom electrode, the resistive material layer having filament features with a filament ratio greater than about 0.5; and a top electrode on the resistive material layer.
    Type: Grant
    Filed: April 28, 2015
    Date of Patent: March 15, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun-Yang Tsai, Yu-Wei Ting, Kuo-Ching Huang
  • Patent number: 9286967
    Abstract: A circuit in dynamic random access memory devices includes a command extension circuit. The command extension circuit is configured to generate at least one multiple-cycle command signal by lengthening a single-cycle clock command signal from a command decoding circuit. Control logic extends and reduces the multiple-cycle command signal to provide additional functions such as burst length and burst chop. Additional control logic is configured to determine whether a clock signal is enabled in output control logic circuitry according to the multiple-cycle command and logic level generated in the output logic circuitry.
    Type: Grant
    Filed: May 7, 2015
    Date of Patent: March 15, 2016
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventors: Debra Bell, Kallol Mazumder
  • Patent number: 9275738
    Abstract: A flash memory device may operate from two supply voltages, one being provided externally, and the other being generated within the flash memory device from the external supply voltage. The flash memory device may be provided with a selectable-level buffer for interfacing with either low supply voltage or high supply voltage integrated circuits. To provide even greater flexibility, the flash memory device may be provided with the capability of receiving a second supply voltage from an external source, which may take precedence over the internally-generated second supply voltage or may be combined with the internally-generated second supply voltage.
    Type: Grant
    Filed: April 27, 2015
    Date of Patent: March 1, 2016
    Assignee: Winbond Electronics Corporation
    Inventors: Jongjun Kim, Eungjoon Park
  • Patent number: 9269414
    Abstract: A semiconductor integrated circuit includes a plurality of semiconductor chips. Each of the plurality of semiconductor chips includes a chip selection unit suitable for generating an internal chip selection signal in response to one or more selective chip selection signals and transferring the selective chip selection signals to an adjacent semiconductor chip of the plurality of semiconductor chips, a selective setting unit suitable for generating a selective internal signal, selectively activated in each semiconductor chip, in response to the internal chip selection signal and an external setting signal, and a common setting unit suitable for generating a common internal signal, activated in common in the plurality of semiconductor chips, in response to the setting signal and an external common chip selection signal.
    Type: Grant
    Filed: December 15, 2013
    Date of Patent: February 23, 2016
    Assignee: SK Hynix Inc.
    Inventors: Jae-Bum Ko, Sang-Jin Byeon
  • Patent number: 9263116
    Abstract: In a memory device, memory capacity per unit area is increased while a period in which data is held is ensured. The memory device includes a driver circuit provided over a substrate, and a plurality of memory cell arrays which are provided over the driver circuit and driven by the driver circuit. Each of the plurality of memory cell arrays includes a plurality of memory cells. Each of the plurality of memory cells includes a first transistor including a first gate electrode overlapping with an oxide semiconductor layer, and a capacitor including a source electrode or a drain electrode, a first gate insulating layer, and a conductive layer. The plurality of memory cell arrays is stacked to overlap. Thus, in the memory device, memory capacity per unit area is increased while a period in which data is held is ensured.
    Type: Grant
    Filed: May 20, 2015
    Date of Patent: February 16, 2016
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Jun Koyama, Shunpei Yamazaki
  • Patent number: 9257154
    Abstract: Apparatuses and methods for compensating for source voltage is described. An example apparatus includes a source coupled to a memory cell and a read-write circuit coupled to the memory cell. The apparatus further includes a sense current generator coupled to a node of the source and to the read-write circuit, the sense current generator configured to control provision of a sense current by the read-write circuit responsive to a voltage of the node of the source.
    Type: Grant
    Filed: November 29, 2012
    Date of Patent: February 9, 2016
    Assignee: Micron Technology, Inc.
    Inventor: Jaekwan Park
  • Patent number: 9245628
    Abstract: A non-volatile semiconductor memory device includes a semiconductor layer of a first conductivity type, and a plurality of wells of a second conductivity type formed on the first semiconductor layer, the wells being arranged in a first direction. A memory block is arranged in each well. A plurality of word lines are provided, each word line being commonly connected to a plurality of NAND cell units in one memory block. A plurality of bit lines extend in a first direction, the bit lines being connected to first ends of the NAND cell units present in the memory blocks. A source line is connected to second ends of the NAND cell units. A well driver performs a control of selectively providing a first voltage or a second voltage higher than the first voltage to each well.
    Type: Grant
    Filed: August 27, 2012
    Date of Patent: January 26, 2016
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventor: Hiroshi Maejima
  • Patent number: 9236138
    Abstract: A semiconductor memory device includes at least one cell string to include a plurality of dummy memory cells and a plurality of memory cells connected in series between the plurality of dummy memory cells; and the peripheral circuit to control the at least one cell string so that a first type of data represented by a first number of bits is stored in at least one of the dummy memory cells and a second type of data represented by a second number of bits, the second number smaller than the first number, is stored in at least two of the plurality of memory cells.
    Type: Grant
    Filed: January 7, 2014
    Date of Patent: January 12, 2016
    Assignee: SK HYNIX INC.
    Inventor: Hee Youl Lee
  • Patent number: 9230622
    Abstract: A method includes generating a first and a second internal clock signal from a clock signal, wherein a first internal clock signal edge of the first internal clock signal and a second internal clock signal edge of the second internal clock signal are generated from a same edge of the clock signal. A first one of the first and the second internal clock edges is used to trigger a first operation on a six-transistor (6T) Static Random Access Memory (SRAM) cell of a SRAM array. A second one of the first and the second internal clock edges is used to trigger a second operation on the 6T SRAM cell. The first and the second operations are performed on different ports of the 6T SRAM. The first and the second operations are performed within a same clock cycle of the clock signal.
    Type: Grant
    Filed: November 30, 2012
    Date of Patent: January 5, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ching-Wei Wu, Chia-Cheng Chen, Kuang Ting Chen, Wei-Shuo Kao, Jui-Che Tsai
  • Patent number: 9227456
    Abstract: A three-dimensional memory is formed as an array of memory elements across multiple layers positioned at different distances above a semiconductor substrate. Cylindrical stacks of memory elements are formed where a cylindrical opening has read/write material deposited along its wall, and a cylindrical vertical bit line formed along its central axis. Memory elements formed on either side of such a cylinder may include sheet electrodes that extend into the read/write material.
    Type: Grant
    Filed: March 7, 2013
    Date of Patent: January 5, 2016
    Assignee: SanDisk 3D LLC
    Inventors: Henry Chien, Yao-Sheng Lee, George Samachisa, Johann Alsmeier
  • Patent number: 9230644
    Abstract: An electronic device includes semiconductor memory, which includes a memory cell block including first and second cell arrays and a column control block. The first cell array includes a word line, a first bit line, and a first variable resistance layer disposed between the word line and the first bit line. The second cell array includes the word line, a second bit line crossing the word line and the first bit line, and a second variable resistance layer disposed between the word line and the second bit line. The first and second variable resistance layers include different materials. The column control block supplies a first write bias for switching a resistance state of the first variable resistance layer to the first bit line and a second write bias for switching a resistance state of the second variable resistance layer to the second bit line.
    Type: Grant
    Filed: August 7, 2014
    Date of Patent: January 5, 2016
    Assignee: SK HYNIX INC.
    Inventor: Hae-Chan Park
  • Patent number: 9224429
    Abstract: According to example embodiments of inventive concepts, a three-dimensional semiconductor device may include: a memory cell array including memory cells that may be arranged three-dimensionally, the memory cell array including a left side opposite a right side, and a top side opposite a bottom side in a plan view; at least one word line decoder adjacent to at least one of the left and right sides of the memory cell array; a page buffer adjacent to the bottom side of the memory cell array; and a string selection line decoder adjacent to one of the top and bottom sides of the memory cell array.
    Type: Grant
    Filed: March 2, 2015
    Date of Patent: December 29, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jintaek Park, Kohji Kanamori, Youngwoo Park, Jaeduk Lee
  • Patent number: 9218891
    Abstract: A data storage device using a FLASH memory with replay-protected blocks. The storage space of the FLASH memory is divided into blocks and each block is further divided into pages. A controller is provided in the data storage device to couple to the FLASH memory. The controller manages at least one replay-protected memory block of the FLASH memory. The controller programs a success flag and a write count into a system block of the FLASH memory after the controller programs two pages into the at least one replay-protected memory block of the FLASH memory. The controller may perform a power restoration process based on the success flag of the system block or/and based on the amount of programmed pages of the at least one replay-protected memory block.
    Type: Grant
    Filed: November 27, 2013
    Date of Patent: December 22, 2015
    Assignee: Silicon Motion, Inc.
    Inventors: Chia-Chien Wu, Yu-Chih Lin, Yen-Hung Lin
  • Patent number: 9214455
    Abstract: A microelectronic package includes a microelectronic element having memory storage array function overlying a first surface of a substrate, the microelectronic element having a plurality of contacts aligned with an aperture in the substrate. First terminals which are configured to carry all address signals transferred to the package can be exposed within a first region of a second substrate surface, the first region disposed between the aperture and a peripheral edge of the substrate. The first terminals may be configured to carry all command signals, bank address signals and command signals transferred to the package, the command signals being write enable, row address strobe, and column address strobe.
    Type: Grant
    Filed: December 22, 2014
    Date of Patent: December 15, 2015
    Assignee: Invensas Corporation
    Inventors: Richard Dewitt Crisp, Wael Zohni
  • Patent number: 9208864
    Abstract: A memory includes cytokines, such as macromolecule proteins, as a poly-state data storage. Each fold state of multiple fold states of a protein are associated with a data value. Current flow through the protein is associated with a resistance of the protein associated with its current fold state. Application of light, electric fields or heat via an associated element or elements facilitates placement of a protein in a fold state that corresponds to an associated resistance and correlates with an incoming data value. Measuring of current or resistance allows for reading of a data value associated with the protein.
    Type: Grant
    Filed: October 14, 2013
    Date of Patent: December 8, 2015
    Assignee: Toshiba America Electronic Components, Inc.
    Inventor: Rakesh Sethi
  • Patent number: 9196323
    Abstract: A memory system includes a controller suitable for providing a data to be written on a memory cell array and a control data for indicating whether or not the data has a preset data pattern and a memory device suitable for selectively writing an patterned data or the data provided by the controller on the memory cell array in response to the control data, wherein the patterned data is stored in the memory device and has the preset data pattern.
    Type: Grant
    Filed: December 15, 2013
    Date of Patent: November 24, 2015
    Assignee: SK Hynix Inc.
    Inventor: Jung-Hyun Kwon
  • Patent number: 9190174
    Abstract: Apparatuses and methods involving the determination of soft data from hard reads are provided. One example method can include determining, using a hard read, a state of a memory cell. Soft data is determined based, at least partially, on the determined state.
    Type: Grant
    Filed: November 30, 2012
    Date of Patent: November 17, 2015
    Assignee: Micron Technology, Inc.
    Inventors: Sivagnanam Parthasarathy, Patrick R. Khayat, Mustafa N. Kaynak