Abstract: A semiconductor device includes a first electrode layer and a second electrode layer disposed over a substrate, a first insulating layer disposed over the first electrode layer, and a reflective electrode layer disposed on the first insulating layer and electrically connected to the first electrode layer, wherein the second electrode layer is exposed externally, and a thickness of the second electrode layer is greater than a thickness of the reflective electrode layer.

Abstract: Embodiments of the present invention are directed to leadframe area array packaging technology for fabricating an area array of I/O contacts. A manufactured package includes a polymer material substrate, an interconnect layer positioned on top of the polymer material substrate, a die coupled to the interconnect layer via wire bonds or conductive pillars, and a molding compound encapsulating the die, the interconnect layer and the wire bonds or conductive pillars. The polymer material is typically formed on a carrier before assembly and is not removed to act as the substrate of the manufactured package. The polymer material substrate has a plurality of through holes that exposes the interconnect layer at predetermined locations and enables solder ball mounting or solder printing directly to the interconnect layer. In some embodiments, the semiconductor package includes a relief channel in the polymer material substrate to improve the reliability performance of the manufactured package.

Abstract: At least one projecting block is formed in an element. The projecting block is then covered with a first cover layer so as to form a concave ridge self-aligned with the projecting block and having its concavity face towards the projecting block. A first trench is then formed in the ridge in a manner that is self-aligned with both the ridge and the projecting block. The first trench extends to a depth which reaches the projecting block. The projecting block is etched using the ridge and first trench as an etching mask to form a second trench in the projecting block that is self-aligned with the first trench. A pattern is thus produced by the second trench and unetched parts of the projecting block which delimit the second trench.

Abstract: The invention provides a method for fabricating a silicon-oxide-nitride-oxide-silicon (SONOS) non-volatile memory cell, comprising: (S1) forming a pad oxide pattern on a silicon substrate having a recess exposing a tunnel region of the silicon substrate; (S2) forming a bottom oxide layer, a nitride layer, a top oxide layer covering the recess and the pad oxide pattern to form a first ONO structure; (S3) forming a photoresist on the first ONO structure covering the recess and a peripheral region of the pad oxide pattern; (S4) removing a part of the first ONO structure exposed by the photoresist to form an U-shaped ONO structure; (S5) trimming the photoresist to exposed a part of the U-shaped ONO structure above the recess; (S6) removing the part of the U-shaped ONO structure; (S7) removing the photoresist; (S8) removing the pad oxide pattern and the top oxide layer; and (S9) forming a gate structure.

Abstract: Provided are approaches of forming a semiconductor device (e.g., transistor such as a FinFET or planar device) having a gate metal recess. In one approach, a liner layer and a metal layer (e.g., W) are applied in a trench (e.g., via CVD and/or ALD). Then, a single chamber (e.g., an extreme fill chamber) will be utilized to separately etch back the liner layer and the metal layer. In general, the liner layer may be etched back further than the metal layer to provide for larger contact and lower resistance. After etching is complete, a bottom-up fill/growth of metal (e.g., W) will be performed (e.g., via CVD in a W chamber or the like) to increase the presence of gate metal in the trench.

Abstract: A method of forming a target pattern includes forming a first trench in a substrate with a cut mask; forming a first plurality of lines over the substrate with a first main mask, wherein the first main mask includes at least one line that overlaps the first trench and is thereby cut into at least two lines by the first trench; forming a spacer layer over the substrate and the first plurality of lines and over sidewalls of the first plurality of lines; forming a patterned material layer over the spacer layer with a second main mask thereby the patterned material layer and the spacer layer collectively define a second plurality of trenches; removing at least a portion of the spacer layer to expose the first plurality of lines; and removing the first plurality of lines thereby resulting a patterned spacer layer over the substrate.

Abstract: A structure includes a substrate having a plurality of balls, a semiconductor chip, and an interposer electrically connecting the substrate and the semiconductor chip. The interposer includes a first side, a second side opposite the first side, at least one first exclusion zone extending through the interposer above each ball of the plurality of balls, at least one active through via extending from the first side of the interposer to the second side of the interposer, wherein the at least one active through via is formed outside the at least one first exclusion zone and wherein no active through vias are formed within the at least one first exclusion zone, and at least one dummy through via extending from the first side of the interposer to the second side of the interposer, wherein the at least one dummy through via is formed within the at least one first exclusion zone.

Abstract: Methods for fabricating guide patterns and methods for fabricating integrated circuits using guide patterns are provided. In an embodiment, a method for fabricating a guide pattern includes forming a coating of a material with latent grafting sites and a photosensitive component configured to activate the latent grafting sites upon exposure over a substrate. The method exposes selected latent grafting sites in the coating to convert the selected latent grafting sites to active grafting sites. A grafting agent is bonded to the active grafting sites to form the guide pattern.

Abstract: Provided is a manufacturing method of an array substrate with an etching stop layer. The method includes: forming a pattern including a gate, a gate line and a common electrode line on a substrate through a first patterning process; forming a gate insulation layer, an active layer film and an etching stop layer through a second patterning process; wherein, the etching stop layer corresponds to a gap between a source and a drain which are to be formed, and a via hole exposing the common electrode line is formed above the common electrode line; forming at least an active layer, a pattern including source, drain and data line and a protection layer through a third patterning process; wherein, the protection layer exposes a part of the drain; and forming at least a pixel electrode through a fourth patterning process; wherein, the pixel electrode is electrically connected with the drain.

Abstract: According to one embodiment, the manufacturing method for the semiconductor device according to the embodiment includes carrying out ion implantation to the semiconductor layer and forming an amorphous layer on the surface of the semiconductor layer, and a heat treatment process using microwave annealing at a temperature higher than or equal to 200° C. and lower than or equal to 700° C. and single crystallizes the amorphous layer.

Abstract: According to an embodiment, a semiconductor device includes at least two control electrodes, a plurality of semiconductor layers and an insulating film. Each control electrode extends in a first direction. The semiconductor layers are provided between the control electrodes, and arranged in the first direction. Each semiconductor layer extends in a second direction orthogonal to the first direction. The insulating film covers side surfaces of the semiconductor layers, and is disposed between the control electrodes. Each semiconductor layer has a side surface that includes at least one curved surface swelling in a direction from a center of the semiconductor layer to the insulating film.

Abstract: A circuit device includes core circuitry. The circuit device further includes a first set of guard rings having a first dopant type, the first set of guard rings being around a periphery of the core circuitry, the first set of guard rings comprising a first guard ring and a second guard ring. The circuit device further includes a second set of guard rings having a second dopant type, the second dopant type being opposite to the first dopant type, wherein at least one guard ring of the second set of guard rings is around a periphery of at least one guard ring of the first set of guard rings, and the second set of guard rings comprises a third guard ring and a fourth guard ring.

Abstract: The method may include forming a plurality of fins on a substrate with first and second regions, forming a photoresist pattern to expose the fins of the first region, forming a material layer to cover the fins of first region and the photoresist pattern, chemically reacting the photoresist pattern the material layer to form a supplemental film on a side surface of the photoresist pattern, performing an ion implantation process using the photoresist pattern and the supplemental film as a ion injection mask to form impurity layers in the fins of the first region.

Abstract: There is provided a method of manufacturing a semiconductor device including: preparing a semiconductor substrate having an active region; forming a dielectric layer for gate insulation on the active region; forming a curing layer with a material containing germanium (Ge) on the dielectric layer; heat-treating the curing layer; and removing the curing layer. The germanium-containing material may be silicon germanium (SiGe) or germanium (Ge).

Abstract: A method of conformally doping a device on a semiconductor workpiece is disclosed. An oxide layer is applied to all surfaces of the device. Further, the thickness of the oxide layer on each surface is proportional to the energy that ions impact that particular surface. For example, ions strike the horizontal surfaces at nearly a normal angle and penetrate more deeply into the workpiece than ions striking the vertical surfaces. After creating an oxide layer that has a variable thickness, a subsequent dopant implant is performed. While ions strike the horizontal surfaces with more energy, these ions pass through a thicker oxide layer to penetrate the workpiece. In contrast, ions strike the vertical surfaces with less energy, but traverse a much thinner oxide layer to penetrate the workpiece. The result is a conformally doped device.

Abstract: A method of forming a semiconductor device includes patterning a first mask over a substrate defining a first opening. The substrate includes a first dopant type. The method includes implanting ions having a second dopant type through the first opening to form a first deep well. The method includes patterning a second mask over the substrate defining a second opening. The method includes implanting ions having the second dopant type through the second opening to form a second deep well, wherein an energy for implanting ions to form the second deep well is lower than an energy for implanting ions to form the first deep well. The method includes implanting ions having the first dopant type into the substrate to form a first well, wherein the energy for implanting ions to form the second deep well is greater than an energy for implanting ions to form the first well.

Abstract: In an aspect, an organic light emitting diode display including: a substrate; a first electrode and an auxiliary electrode positioned on the substrate and separated from each other; an absorption electrode positioned on the auxiliary electrode; an organic emission layer positioned on the first electrode and having a contact hole exposing the auxiliary electrode and the absorption electrode; and a second electrode positioned on the organic emission layer and connected to the auxiliary electrode and the absorption electrode through the contact hole is provided. In an aspect, the organic light emitting diode (OLED) display may minimize the voltage drop of the driving power passing through the large-sized electrode of the thin film for driving the organic emission layer, and may simplify the removal process of the organic emission layer on the auxiliary electrode by adding the absorption electrode on the auxiliary electrode.

Abstract: The present invention provides a method for producing a silicon wafer including a step of, after growing the oxide film on one surface of a raw material silicon wafer by chemical-vapor deposition, performing double-side polishing of the raw material silicon wafer in such a manner that a suede polishing pad or a velour polishing pad with an asker-C rubber hardness of 50° or more but less than 90° is used for the oxide-film surface.

Abstract: A semiconductor device has an on-die decoupling capacitor that is shared between alternative high-speed interfaces. A capacitance pad is connected to the decoupling capacitor and internal connection pads are connected respectively to the alternative interfaces. Internal connection bond wires connect the decoupling capacitor to the selected interface through the capacitance pad and the internal connection pads in the same process as connecting the die to external electrical contacts of the device.

Abstract: A manufacturing method of an oxide semiconductor device includes the following steps. A barrier layer is formed on a substrate. An annealing process is performed after the step of forming the barrier layer. A first oxygen treatment is performed on the barrier layer after the annealing process for forming a first oxygen provider layer on the barrier layer. An oxide semiconductor layer is then formed on the first oxygen provider layer.