Patents Examined by Pamela E Perkins
  • Patent number: 9412943
    Abstract: An organic molecular memory in an embodiment includes a first conductive layer; a second conductive layer; and an organic molecular layer provided between the first conductive layer and the second conductive layer, the organic molecular layer including an organic molecule having an oligophenylene ethynylene backbone, the oligophenylene ethynylene backbone including three or more benzene rings, and the oligophenylene ethynylene backbone including two fluorine atoms added in ortho positions or meta positions of one of the benzene rings other than benzene rings at both ends.
    Type: Grant
    Filed: September 1, 2015
    Date of Patent: August 9, 2016
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Koji Asakawa, Yutaka Majima, Hideyuki Nishizawa, Yusuke Tanaka, Shigeki Hattori
  • Patent number: 9412769
    Abstract: Example embodiments relate to a transistor, a method of manufacturing a transistor, and/or an electronic device including the transistor. In example embodiments, the transistor includes a first field effect transistor (FET) and a second FET connected in series to each other, wherein a first gate insulating film of the first FET and a second gate insulating film of the second FET have different leakage current characteristics or gate electric field characteristics.
    Type: Grant
    Filed: August 4, 2014
    Date of Patent: August 9, 2016
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Kyoung-seok Son, Sun-jae Kim, Tae-sang Kim
  • Patent number: 9406905
    Abstract: An organic light-emitting display apparatus includes a flexible substrate. The organic light-emitting display apparatus includes a first plastic layer. A first barrier layer is formed on the first plastic layer. A second plastic layer is formed on the first barrier layer. An organic light-emitting device layer is formed on the second plastic layer. A thin film encapsulating layer encapsulates the organic light-emitting device layer. The first barrier layer is patterned to correspond to an area where the organic light-emitting device layer is formed.
    Type: Grant
    Filed: March 14, 2014
    Date of Patent: August 2, 2016
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Yong-Hwan Park, Jae-Seob Lee, Yong-Kwan Kim, Chung Yi
  • Patent number: 9401465
    Abstract: The present invention includes an N-type semiconductor layer, an active layer, a P-type semiconductor layer, a metal mirror layer, a protection adhesive layer and a metal buffer layer that are sequentially stacked. The protection adhesive layer is selected from a group consisting of a metal oxide and a metal nitride, fully covers one side of the metal mirror layer away from the P-type semiconductor layer, and includes a plurality of conductive holes. The metal buffer layer penetrates through the conductive holes to be electrically connected to the metal mirror layer. After forming the metal mirror layer on the P-type semiconductor layer, the protection adhesive layer that fully covers the metal mirror layer is directly formed to thoroughly protect the metal mirror layer by using the protection adhesive layer, thereby maintaining a reflection rate of the metal mirror layer and ensuring light emitting efficiency of a light emitting diode.
    Type: Grant
    Filed: October 17, 2014
    Date of Patent: July 26, 2016
    Assignee: HIGH POWER OPTO. INC.
    Inventors: Wei-Yu Yen, Li-Ping Chou, Fu-Bang Chen, Chih-Sung Chang
  • Patent number: 9397220
    Abstract: A thin film transistor disposed on a substrate is provided. The thin film transistor includes a channel, a gate, a source, a drain and an etching stop layer. The channel is disposed above the substrate and is located between the etching stop layer and the source. The gate is disposed on the substrate and overlapped with the channel. The source is disposed between the channel and the substrate and electrically connected to the channel. The channel is disposed between the drain and the substrate. The etching stop layer is disposed between the drain and the channel and has a first through hole exposing a portion of the channel. The drain is filled in the first through hole of the etching stop layer and is electrically connected to the channel. The drain covers the channel completely.
    Type: Grant
    Filed: August 24, 2014
    Date of Patent: July 19, 2016
    Assignee: Chunghwa Picture Tubes, LTD.
    Inventors: Chin-Hai Huang, Chieh-Wei Feng, Szu-Chi Huang, Kune-Yu Lai, Yen-Yu Huang
  • Patent number: 9396929
    Abstract: Provided are: forming a thin film made of a specific element alone on a substrate by performing a specific number of times a cycle of: supplying a first source to the substrate, the first source containing the specific element and a halogen-group; and supplying a second source to the substrate, the second source containing the specific element and an amino-group, and having amino-group-containing ligands whose number is two or less in its composition formula and not more than the number of halogen-group-containing ligands in the composition formula of the first source.
    Type: Grant
    Filed: September 9, 2013
    Date of Patent: July 19, 2016
    Assignees: HITACHI KOKUSAI ELECTRIC INC., L'AIR LIQUIDE, SOCIETE ANONYME POUR L'ETUDE ET L'EXPLOITATION DES PROCEDES GEORGES CLAUDE
    Inventors: Yoshiro Hirose, Norikazu Mizuno, Kazutaka Yanagita, Katsuko Higashino
  • Patent number: 9391018
    Abstract: Transmission lines with a first dielectric material separating signal traces and a second dielectric material separating the signal traces from a ground plane. In embodiments, mutual capacitance is tuned relative to self-capacitance to reverse polarity of far end crosstalk between a victim and aggressor channel relative to that induced by other interconnect portions along the length of the channels, such as inductively coupled portions. In embodiments, a transmission line for a single-ended channel includes a material of a higher dielectric constant within the same routing plane as a microstrip or stripline conductor, and a material of a lower dielectric constant between the conductor and the ground plane(s). In embodiments, a transmission line for a differential pair includes a material of a lower dielectric constant within the same routing plane as a microstrip or stripline conductors, and a material of a higher dielectric constant between the conductors and the ground plane(s).
    Type: Grant
    Filed: February 3, 2014
    Date of Patent: July 12, 2016
    Assignee: Intel Corporation
    Inventors: Zhichao Zhang, Tolga Memioglu, Tao Wu, Kemal Aygun
  • Patent number: 9391205
    Abstract: A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a substrate and a metal gate structure formed over a fin structure of the substrate. The semiconductor structure further includes a spacer formed on a sidewall of the metal gate structure and a source/drain structure formed in the fin structure. In addition, the spacer is in direct contact with the fin structure.
    Type: Grant
    Filed: October 17, 2014
    Date of Patent: July 12, 2016
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD
    Inventors: Che-Cheng Chang, Chih-Han Lin, Jr-Jung Lin
  • Patent number: 9391227
    Abstract: A substrate includes a first region having photoelectric conversion portions and a second region having an element included in a signal processing circuit. An insulator including first and second parts respectively arranged on the first and second regions is formed on the substrate. Openings are formed in the insulator and respectively superposed on the photoelectric conversion portions. A first member is formed in the openings and on the second part of the insulator after forming the openings. At least a portion of the first member arranged on the second region is removed. The first member is planarized after removing at least the portion of the first member. A second insulator is formed on the first and second regions after planarizing the first member. A through-hole is formed in a part of the second insulator. No planarization with grinding is performed after forming the second insulator and before forming the through-hole.
    Type: Grant
    Filed: August 5, 2013
    Date of Patent: July 12, 2016
    Assignee: Canon Kabushiki Kaisha
    Inventors: Tadashi Sawayama, Takashi Usui, Akihiro Kawano, Hiroaki Naruse, Sho Suzuki, Takehito Okabe, Masatsugu Itahashi, Daisuke Uki
  • Patent number: 9385263
    Abstract: A method for producing a dopant profile is provided. The method includes starting from a surface of a wafer-shaped semiconductor component by introducing dopant atoms into the semiconductor component. The dopant-containing layer is produced on or in a region of the surface in order to produce a provisional first dopant profile and then a plurality of semiconductor components having a corresponding layer is subjected to heat treatment on top of one another in the form of a stack in order to produce a second dopant profile having a greater depth in comparison to the first dopant profile.
    Type: Grant
    Filed: December 3, 2009
    Date of Patent: July 5, 2016
    Assignee: SCHOTT SOLAR AG
    Inventors: Joerg Horzel, Dieter Franke, Gabriele Blendin, Marco Faber, Wilfried Schmidt
  • Patent number: 9384964
    Abstract: The inventive concepts provide methods of manufacturing a semiconductor device including a thermal treatment process. The method may include providing a substrate including a channel region of a transistor, forming an initial oxide layer on the channel region, and performing a thermal treatment process at least once before or after forming the initial oxide layer.
    Type: Grant
    Filed: August 1, 2014
    Date of Patent: July 5, 2016
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Yongkuk Jeong, Hyeonbeom Gwon, Junghwa Seo
  • Patent number: 9385048
    Abstract: The present invention provides a method of forming Fin-FET. A substrate with an active region and a dummy region are defined thereon. A plurality of first fins and second fins are formed in the active region, and a plurality of dummy fins are formed in the dummy region and the active region. A first active region is provided in the active region. A revised first active region is formed by extending the first active region to cover at least one adjacent dummy fin. Next, a first dummy region is provided in the dummy region. A first mask layout is formed by combining the revised first active region and the first dummy region. A first patterned mask layer is formed by using the first mask layout. A first epitaxial process is performed for the first fins and the dummy fins exposed by the first patterned mask layer.
    Type: Grant
    Filed: September 5, 2013
    Date of Patent: July 5, 2016
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Shih-Fang Hong, Chung-Yi Chiu
  • Patent number: 9385199
    Abstract: A method includes forming a relaxed layer in a semiconductor device. The method also includes forming a tensile layer over the relaxed layer, where the tensile layer has tensile stress. The method further includes forming a compressive layer over the relaxed layer, where the compressive layer has compressive stress. The compressive layer has a piezoelectric polarization that is approximately equal to or greater than a spontaneous polarization in the relaxed, tensile, and compressive layers. The piezoelectric polarization in the compressive layer could be in an opposite direction than the spontaneous polarization in the compressive layer. The relaxed layer could include gallium nitride, the tensile layer could include aluminum gallium nitride, and the compressive layer could include aluminum indium gallium nitride.
    Type: Grant
    Filed: June 30, 2014
    Date of Patent: July 5, 2016
    Assignee: NATIONAL SEMICONDUCTOR CORPORATION
    Inventor: Jamal Ramdani
  • Patent number: 9385342
    Abstract: An electroluminescent display or lighting product incorporates a panel comprising a collection of distinct light-emitting elements formed on a substrate. A plurality of distinct local seals are formed over respective individual light-emitting elements or groups of light-emitting elements. Each local seal is formed by depositing a low melting temperature glass powder suspension or paste, and fusing the glass powder. Fusing may be performed using selective heating by microwave or laser irradiation. Energy absorption may be enhanced by incorporating absorbing particles in the glass powder paste or suspension. The local seal may be used in conjunction with a continuous thin film encapsulation structure. Optical functions can be provided by each local seal, including refraction, filtering, color shifting, and scattering.
    Type: Grant
    Filed: April 24, 2015
    Date of Patent: July 5, 2016
    Assignee: Global OLED Technology LLC
    Inventor: Rajeev Rohatgi
  • Patent number: 9379213
    Abstract: Method for fabricating a transistor comprising the steps consisting of: forming sacrificial zones in a semi-conductor layer, either side of a transistor channel zone, forming insulating spacers on said sacrificial zones against the sides of the gate of said transistor, removing said sacrificial zones so as to form cavities, with the cavities extending on either side of said channel zone and penetrating under said spacers, forming doped semi-conductor material in said cavities, with said semi-conductor material penetrating under said spacers.
    Type: Grant
    Filed: August 4, 2014
    Date of Patent: June 28, 2016
    Assignees: Commissariat a l'energie atomique et aux energies alternatives, STMICROELECTRONICS SA
    Inventors: Perrine Batude, Jean-Michel Hartmann, Benoit Sklenard, Maud Vinet
  • Patent number: 9362491
    Abstract: A semiconductor process integrates three bridge circuits, each include magnetoresistive sensors coupled as a Wheatstone bridge on a single chip to sense a magnetic field in three orthogonal directions. The process includes various deposition and etch steps forming the magnetoresistive sensors and a plurality of flux guides on one of the three bridge circuits for transferring a ā€œZā€ axis magnetic field onto sensors orientated in the XY plane.
    Type: Grant
    Filed: November 30, 2015
    Date of Patent: June 7, 2016
    Assignee: EVERSPIN TECHNOLOGIES, INC.
    Inventors: Renu Whig, Phillip Mather, Kenneth Smith, Sanjeev Aggarwal, Jon Slaughter, Nicholas Rizzo
  • Patent number: 9356213
    Abstract: A manufacturing method of a light-emitting diode device. The light-emitting diode device comprises: a substrate (1); an epitaxial layer at one side of the substrate (1) and comprising an N-type layer (2), a P-type layer (4), and an active layer (3) between the N-type layer (2) and the P-type layer (4); an N-type electrode (5); a P-type electrode (7); an adhesive layer (8); and a patterned substrate (9). The light-emitting diode device further comprises an insulating layer (6) between the N-type electrode (5) and the P-type electrode (7), the insulating layer (6) electrically insulating the N-type electrode (5) and the P-type electrode (7). In the manufacturing method thereof, light-emitting efficiency and luminous efficiency of the light-emitting diode device can be improved, wiring is easier as compared with conventional chips, and the manufacturing process can be optimized.
    Type: Grant
    Filed: September 23, 2015
    Date of Patent: May 31, 2016
    Assignee: WUXI CHINA RESOURCES HUAJING MICROELECTRONICS CO., LTD.
    Inventors: Lei Wang, Guoqi Li, Zhiyan Yu, Rongsheng Pu
  • Patent number: 9356038
    Abstract: A semiconductor device and a method of fabricating the same are provided. The semiconductor device includes insulating layers stacked in the shape of stairs, and conductive layers alternately stacked with the insulating layers, wherein the conductive layers each include a first region interposed between upper and lower insulating layers thereof, among the insulating layers, and a second region which extends from the first region and protrudes between the upper and lower insulating layers, and wherein a protruding part formed on a sidewall or an upper surface of the second region.
    Type: Grant
    Filed: August 21, 2014
    Date of Patent: May 31, 2016
    Assignee: SK Hynix Inc.
    Inventors: Ki Hong Lee, Seung Ho Pyi, Seok Min Jeon
  • Patent number: 9337313
    Abstract: A structure includes a substrate having an insulator layer and a plurality of elongated semiconductor fin structures disposed on a surface of the insulator layer. The fin structures are disposed substantially parallel to one another. The structure further includes a plurality of elongated sacrificial gate structures each comprised of silicon nitride. The sacrificial gate structures are disposed substantially parallel to one another and orthogonal to the plurality of fin structures, where a portion of each of a plurality of adjacent fin structures is embedded within one of the sacrificial gate structures leaving other portions exposed between the sacrificial gate structures. The structure further includes a plurality of semiconductor source/drain (S/D) structures disposed over the exposed portions of the fin structures between the sacrificial gate structures. The embodiments eliminate a need to form a conventional spacer on the fin structures.
    Type: Grant
    Filed: September 16, 2013
    Date of Patent: May 10, 2016
    Assignee: GLOBALFOUNDRIES INC.
    Inventor: Effendi Leobandung
  • Patent number: 9331456
    Abstract: A method of manufacturing a semiconductor laser according to an aspect of the present invention includes (a) sequentially epitaxially growing a first cladding layer, an active layer and a second cladding layer on a semiconductor substrate composed of InP or GaAs and having a plane index of (100), (b) forming a plurality of growth start surfaces having a plane index greater than (100) in an upper surface of the second cladding layer, and (c) epitaxially growing a third cladding layer containing zinc in the plurality of growth start surfaces of the second cladding layer.
    Type: Grant
    Filed: July 29, 2014
    Date of Patent: May 3, 2016
    Assignee: Sumitomo Electric Device Innovations, Inc.
    Inventor: Masami Ishiura