Abstract: A computer-implemented method and apparatus for determining the availability of a computer network includes a computer program which receives outage signals that are representative of outages of network devices and network device interfaces, in the event that a particular device has more than one network interface. Also, the program receives online signals on a periodic basis and based on the online signals, determines the average number of online interface-minutes during a subset of a preselected period. Then, the number of outage minutes is divided by the average number of online interface-minutes and substracted from one, to generate an availability signal which can be output as an indication of network availability during the preselected period.

Abstract: A microprocessor detects a floating point exchange instruction followed by a floating point instruction and dispatches the two instructions to the floating point unit as one combined instruction. The predecode unit marks the two instructions as a single instruction. A start bit is asserted for the first byte of the floating point exchange instruction and an end bit is asserted for the last byte of the floating point instruction. The combined instruction is dispatched into the instruction execution pipeline. A decode unit decodes the opcodes of the two instructions and passes the opcode of the floating point instruction to the floating point unit and passes exchange register information to the floating point unit. The exchange register information includes a sufficient number of bits to specify a floating point register and a valid bit.

Abstract: An instruction queue 80 maintains the CPI (clock cycles per instruction) and performance of a microprocessor that employs the instruction queue even if a branch instruction is executed. The queue 80 stores valid instructions in an instruction memory 810. When a branch instruction is supplied to the queue 80, the queue 80 detects instructions that are independent of the branch instruction in the memory 810, and an order controller 1300 puts the independent instructions behind the branch instruction in the memory 810. The queue 80 quickly finds a branch instruction, to let a cache start refilling speedily. While the cache is being refilled, the independent instructions put behind the branch instruction are executed to improve the CPI.

Abstract: A system and method for controlling the execution rate of an instruction processor on an instruction-by-instruction basis in a data processing system. The user controls the execution rate by specifying "cycle-slip" data for each instruction type in the instruction set. This cycle-slip data is used to force the instruction processor to idle for the specified number of execution cycles during the execution of the associated instruction type, thereby slowing down the rate of execution. Allowing rate control data to be unique for each instruction type allows temporary fixes to be implemented when timing-related hardware problems are discovered during system test. If desired, a uniform number of cycle slips can be imposed on all instructions so that the overall rate of the instruction processor is tailored to match the execution rate of slower peripheral devices.

Abstract: A system and method for performing scanning operations using a scanner connected to a server computer and transmitting acquired images from the scanner server to a client computer. A scan-to-application process is utilized which allows control of the scanner or other image acquiring device which is connected to a scanner server using a virtual TWAIN driver which interfaces to an application program running in the client computer. Image files are also transmitted to a local file storage device of the client computer using a scan-to-file operation. A network protocol is used to implement both the scan-to-application and scan-to-file operation. Computer memories are utilized to store data structures or tables containing various information utilized during the file transfer procedures. Computer memories are also used to buffer and store the protocol packet headers and transmitted information.

Abstract: Live pointer information for a stream of bytecodes is precomputed for each bytecode. The precomputed full live pointer information is stored only for bytecodes at predetermined intervals in the stream. Between the bytecodes for which full live pointer information is stored, changes in the live pointer information produced by each bytecode are encoded using a suitable compressive coding and stored. Later, when a program which needs the live pointer information, such as garbage collection, is initiated, the full live pointer information for the nearest bytecode preceding the desired bytecode boundary is retrieved along with the intervening coded changes. The changes are decoded and applied to the retrieved live pointer information to generate the live pointer information at the desired bytecode boundary.

Abstract: An information processing device, including a main processor and a coprocessor for processing data according to instructions stored in memory, which is composed of an instruction bus for transmitting instructions from memory to the main processor and coprocessor; a first bus used for transmitting data from the main processor to the coprocessor; a second bus used for transmitting data from the coprocessor to the main processor; instruction detecting means for detecting coprocessor calculation instructions out of the instructions received from memory; operand identifying means for identifying source registers and destination registers specified by operands in a detected instruction; data supplying means for supplying data from the identified source registers to the coprocessor via the first bus; data storing means for storing coprocessor calculation results in the identified destination registers; coprocessor instruction detecting means for detecting coprocessor calculation instructions out of all of the instru

Abstract: A data transfer system and method for copying an operating system from an original hard drive to a replacement hard drive such that the replacement hard drive can be substituted for the original hard drive in a self-initializing manner. The system includes a data transfer program that identifies the operating system on the original hard drive. The data transfer program prepares the operating system for copying to the replacement hard drive and then copies the operating system, including all files of the operating system, to the replacement hard drive. After the operating system is copied onto the replacement hard drive, the replacement hard drive can be substituted for the original drive, and the replacement hard drive will be operable in a self-initializing manner.

Abstract: The present data processing apparatus effects the pipeline operation for each of the machine cycle time with a plurality of pipeline stages processed in parallel. With respect to a load & extension instruction for instructing with the single instruction a first processing portion for reading the data shorter than the register length from RAM 19 and a second processing portion for zero-extending or the sign-extending the data into the register length, a zero-extension or a sign-extension operation in the second processing operation is executed, in a pipeline stream different from the pipeline stream where a first processing operation is executed or in a pipeline stage different from the pipeline stage where the reading from the storage portion of the first processing operation is executed.

Abstract: An information processing system continues communication without affecting the operation of an application when a communication line is disconnected due to a communication error. When the application sends a communication connection request to another system, an MS Manager portion connects the application via a communication line. An MS portion sends a control handle, instead of a communication line handle, to the application. When the application sends data, the MS portion changes the control handle appended to the data to the handle of the actual communication line. When data is received from another system, the MS portion changes the handle of the actual communication line to the control handle and passes the control handle to the application. When the communication line is disconnected due to an error, the MS Manager portion connects the application to the other system via another communication line. The MS portion re-sends data not yet received by the other system if there are any.

Abstract: An apparatus for and method of providing a data processing system that delays the writing of an architectural state change value to a corresponding architectural state register for a predetermined period of time. This may provide the instruction processor with enough time to determine if the architectural state change is valid before the architectural state change is actually written to the appropriate architectural state register.

Abstract: Current tools for processing e-mail and other messages do not adequately recognize and manipulate threads, i.e., conversations among two or more people carried out by exchange of messages. The present invention utilizes the textual context and characteristics of messages in order to provide a more reliable and effective way to construct message threads. In accordance with the present invention, statistical information retrieval techniques are used in conjunction with textual material obtained by "filtering" of messages to achieve a significant level of accuracy at identifying when one message is a reply to another.

Abstract: An inexpensive image communication apparatus allows an external information processing terminal to be connected thereto, and uses an interface capable of high-speed data transfer for communication with the PC. The image communication apparatus receives an instruction from the external information processing terminal through an interface control unit in a state in which reception can be performed. When an instruction from the information processing terminal is received while communication is preformed by a communication unit and an instruction from an operation panel is received, the image communication apparatus outputs information indicating that the instruction cannot be executed, in a state in which the interface control unit can perform transmission.

Abstract: Vector data buffer apparatus for interfacing processor bus and register having different word sizes. The vector data buffer includes a word buffer for positioning data words into any desired position by rotation or reverse loading. Endian buffer further provides byte rotation and selectable endian word formation. Latches and selection multiplexers provided for shifting bytes into a wide register to effect register access with only a single processor I/O operation for improved performance of the processor.

Abstract: A method and apparatus for dynamically predicting the outcome and the tar address of a multiple-target branch instruction, where the multiple-target branch instruction contains at least two potential target addresses, not including the fall through address. In addition, this method and apparatus can also be used to predict multiple single-target branches simultaneously. The apparatus stores information indicating the outcome of previous executions and predictions of the multiple-target branch instruction in a branch prediction table. In addition, multiple target addresses (at least two) are associated with the multiple-target branch instruction. Using the information indicating the outcome of the previous execution of the multiple-target branch instruction, the apparatus predicts the outcome of a next execution of the multiple-target branch instruction, and predicts which, if any, of the target addresses associated with the multiple-target branch instruction, will be taken.

Abstract: A communication controller at the sending computer divides data transferred from a host into sub-ACK unit packets and transfers them sequentially to a destination without waiting for the sub-ACK's being subsequently provided by the destination. A communication controller at the receiving computer issues a sub-ACK to the sending computer for each of the sub-ACK unit packet, if the sub-ACK packet has been normally received and otherwise issues retransmission request for the sub-ACK unit packets and merges data included in the sub-ACK unit packets into the initial data, after they are normally received.

Abstract: A method and apparatus that allows a Web page designer to specify that an audio file linked to a Web page should be prefetched before user input is accepted. Web browser software prefetches the audio file if there is enough room in a temporary memory to store the file. The invention also allows a Web page designer to specify the text over which the user must place the cursor to play the audio file. When the temporary memory is full and an audio file needs to be prefetched, the browser deletes files from the temporary memory until there is enough room in the temporary memory for the prefetched audio file. Files are deleted in a least-recently-referenced, first-out order.

Abstract: A method for transporting Internet Protocols (IP's) over an Asynchronous Transfer Mode (ATM) network that exhibits the strengths of ATM, namely packet interleaving (using cell-based transport) with Quality of Service support for connection-oriented traffic (such as multiclass native ATM traffic and flows-based IP traffic using RSVP), while optimizing the connectionless requirements of existing IP traffic. Advantageously, both the IP protocol stack and ATM protocol stack operate as peers over ATM cell transport hardware. The method exploits an "implicit" signaling/control phase characteristic of IP traffic/protocols thereby minimizing setup. The implicit signaling phase is used to map a flow from a routed path to a switched path immediately upon transmission of a first packet. Similarly, particular packets may be immediately transported over the routed path even after establishment of the switched path.

Abstract: A superscalar microprocessor includes a reorder buffer to correctly handle dependency checking and multiple updates to the same destination. The reorder buffer stores instructions in program order, and retires instructions that have executed and the results obtained. When a instruction is retired, the results of the instruction are stored and the memory space in the reorder buffer is deallocated. The results of the retired instructions are stored to a register file via a retire bus. If the results of two or more retired instructions output to the same register in the register file, then only the newest instruction, the later instruction in the original program sequence, is stored to the program register. The register file has a plurality of write ports for the transfer of data via the retire bus. If two retired instructions output to the same register, then a write port is not utilized. The retire window is the number of instructions monitored for retirement.

Abstract: A microprocessor employing a reorder buffer is configured with fixed, symmetrical issue positions. The symmetrical nature of the issue positions may increase the average number of instructions to be concurrently dispatched and executed by the microprocessor. In one embodiment, the reorder buffer allocates a line of storage sufficient to store instruction results corresponding to a maximum number of concurrently dispatchable instructions regardless of the number actually dispatched. The average number of unused locations within the line decreases as the average number of concurrently dispatched instructions increases.