Abstract: A buffer IC includes two FIFO buffers accessible in a triple-bus configuration including a bi-directional port, an input port, and an output port. Each of the ports uses a fall-through timing which facilitates interconnection of similar buffer ICs into a chain to expand the depth of a FIFO buffer. Typically, the input and output ports have a data width that differs from the data width of the bi-directional bus the FIFO buffers perform bus matching. One type of bus matching collects data values from the smaller width port to form larger width values for output from the larger port. Another type of bus matching splits data values from the larger width port to form data values for output from the smaller port.

Abstract: A device control apparatus includes a request accepting unit which accepts a device control request, the device control request containing an instruction code indicating a specified instruction and a device identifier indicating a specified device. A competition control unit includes a set of competition definition tables for respective devices and respective device-control instructions, reads out one of the competition definition tables by the device control request, and recognizes competition states between in-process instructions to competition devices and the specified instruction to the specified device by using the read-out competition definition table. A parallel execution control unit performs execution of one or a plurality of the specified instruction and the in-process instructions in accordance with the competition states when a sum of a first weight for the specified instruction and a second weight for the in-process instructions is less than a maximum weight.

Abstract: A microprocessor having a microcode unit is provided. Routines comprising DSP functions and instruction emulation routines are stored within a read-only memory within the microcode unit. The routines may be fetched by the microprocessor upon occurrence of a corresponding instruction. For example, DSP functions may be fetched upon occurrence of an instruction defined by the microprocessor to be indicative of a DSP function. The microcode unit provides a library of useful functions. Effectively, the instruction set executed by the microprocessor is increased. A number of methods for defining instructions indicative of a DSP function are contemplated. For example, a subroutine call instruction having a target address within a predefined range of addresses may be defined as indicative of a DSP function. Alternatively, a special subroutine call instruction may be added to the instruction set.

Abstract: First and second circuits store therein source and destination operand addressing information from an instruction code as input information of a main decoder, respectively. A third circuit stores therein information other than operand addressing information from the instruction code as input information of the main decoder. A predecoder analyzes the instruction code and controls states of the first, second and third circuits. A first selector determines which information is input to the main decoder, from the first circuit, the second circuit or the third circuit. A processing selecting circuit causes the first selector to select information for each instruction, in a basic sequence of the first circuit, the second circuit and then the third circuit.

Abstract: A testing apparatus designed to check the completion of a command issued earlier in a multiprocessing system having a plurality of nodes. During an initialization phase, each command has been identified by a handle and a record containing the task to be performed asynchronously had been established. When a request for checking the completion of a command is issued, the pre-established record is simply checked for location of last task executed and completed. If the last or most current task is not the last task before the completion of the total command, the user application can choose to either continue the operation of command processing or permanently or temporarily abandon it.

Abstract: A distance learning system consists of a plurality of multi-cast clients of various classes and priorities with one multi-cast client as a primary multi-cast client, a multi-cast server, arbitrator and a distance learning session coordinator. The primary multi-cast client provides the default or primary Audio-Visual Material (AVM) stream. The Multi-Cast Server (MCS) setups a multi-cast over a point to multi-point connection which connects all multi-cast clients that are to take part in a particular distance learning session, along with the Primary multi-cast client. Additionally, the primary multi-cast client is connected to the MCS via a point-to-point link. The multi-cast clients and the primary multi-cast client receive an AVM material stream from the multi-cast server via the point to multi-point connection. When a multi-cast client wishes to speak, a speaking request is sent to the arbitrator, the arbitrator determines whether to grant or deny the speaking request.

Abstract: A number of storage units and a number of state machines are provided to reorder interleaved ATM data cells for a number of channels incoming to a networked host computer. The storage units store the incoming ATM data cells, a number of data structures tracking the stored ATM data cells for the channels and the free resources, and an unload schedule queue. The state machines load and unload the incoming ATM data cells, and update the tracking data structures and schedule queue accordingly.

Abstract: A method, apparatus and computer program product for reducing the data transmitted over an external communication link from a first application resident in a first computer to a second application resident in a second computer. The method, apparatus and computer program product include storing a data stream from the first application to be provided to the second application in response to a request from the second application in a cache resident in the first computer to create a server base cache entry and in a cache resident in the second computer to create a client base cache entry. Requests from the second application are interrogated to determine if a client base cache entry corresponding to the interrogated request exists and to determine if a server base cache entry corresponding to the interrogated request exists.

Abstract: A method, apparatus, and article of manufacture for monitoring and regulating access to a database. Requests for the database are intercepted and evaluated against one or more restrictions established by a database administrator for the database and generating an indication signal representative of the evaluation. The intercepted requests are rejected or allowed in accordance with the indication signal.

Abstract: An apparatus (e.g. a microarchitecture of a microprocessor) comprising a plurality of tags associated with a first storage area indicating that locations in the first storage area are either empty or non-empty responsive to execution of floating point instructions which modify data contained in the first storage area. A first circuit is coupled to the plurality of tags which sets only the plurality of tags to an empty state responsive to receipt of a first instruction. The first instruction indicates termination of execution of instructions which operate upon the packed data stored in the first storage area. The apparatus further comprises a second circuit coupled to the plurality of tags for setting the plurality of tags to a non-empty state responsive to receipt of a second instruction (or instructions). The second instruction specifies an operation upon packed data stored in the first storage area.

Abstract: If an information item tried to be accessed during traveling is stored in a memory unit, an identifier indicating the information item is registered in an unaccessed-information management unit. If, on the other hand, the information item is stored in the memory unit, the information item is displayed and the identifier is registered in an old information access management unit. When a portable information processing apparatus has come to be able to be connected to a network, an information item indicated by the identifier registered in the unaccessed-information management unit is taken in from a server. Further, whether or not the information item indicated by the identifier registered in the old information access management unit is of an updated version is determined on the basis of the storage date of the information item and the creation date of the information item stored in the server and indicated by the identifier.

Abstract: A microprocessor which supports two distinct instruction-set architectures. The microprocessor includes a mode control unit which enables extensions and/or limitations to each of the two architectures and controls the architectural context under which the microprocessor operates. The control unit controls memory management unit (MMU) hardware that is designed to allow address translation to take place under the control of a mode bit so that the translation mechanism can be switched from one architecture to another. A single MMU translates addresses of the two distinct architectures under control of the mode bit which is also used to simultaneously inform instruction decode which architecture is being used so that instructions are properly decoded. The MMU is also capable of mapping the address translation of one architecture onto that of the other so that software written for both architectures may be multi-tasked under the control of a single operating system.

Abstract: A communication system which includes a plurality of information processing units connected to a network. Each information processing unit includes a database for storing information. A duplicate of the information is distributed to each of the other information processing units. Moreover, each information processing unit modifies the information in its database, extracts a differential of the information before modification and the information after modification, and transfers the differential to each of the other information processing units.

Abstract: A micro-code sequencer apparatus (10) and method includes a state machine controller (14) and an instruction memory (24) for executing instructions and branches. The branch conditions for each state are stored in the state machine controller (14) whereas reprogrammable calculation instructions are stored in instruction memory (24). The instruction memory (24) is accessed by a program counter (20) which receives the decoded state information to determine the location of its instruction. A processor (30) processes the instruction and sends the output to a next state decoder (32) which determines the next state based on the branch conditions.

Abstract: A system for managing virtual circuits and determining proper routing of packets in a network environment. The network includes a connection-oriented subnetwork and an arrangement of routers coupled to the connection-oriented subnetwork. The system determines paths to each exit router by considering all possible paths through the connection-oriented subnetwork. The system also determines paths to each exit router by considering existing virutal circuits through the connection-oriented subnetwork. Finally, the system determines and establishes a most beneficial new virtual circuit for the network. Additionally, the rate at which new virtual circuits are established may be regulated by the system.

Abstract: A program is rerun up to an abnormal point. In this situation, a control flow at a division point between a normal point and the abnormal point is derived while a variable influencing the error and the value of the variable at the division point are derived on the basis of four dependences. A programmer determines an error of the control flow, an error of the value of the variable influencing the error, and an error of a value of a variable used in a conditional instruction/loop instruction. Such processing is repeated, so that an instruction finally remaining between the normal and abnormal points is determined to be a bug. If no instruction having a dependence on the abnormal point is present between the normal and abnormal points, a determination is made that a bug related to omission of an instruction is present between the normal and abnormal points.

Abstract: A method and apparatus for executing a misaligned load. The method begins with receiving a load request to load data from a first memory location. An entry in a store buffer is tested to determine whether the entry corresponds to the first memory location. The entry is also tested to determine whether the entry corresponds to a second memory location subsequent to the first memory location. The load request is blocked if the entry corresponds to the first memory location or the second memory location. After a store operation for the store buffer entry is executed, the load request may be unblocked. The apparatus is a processor or a computer system comprising a load buffer capable of storing a load request address in response to a load request. The processor includes an incrementing circuit that generates an incremented load request address. The processor also includes a store buffer containing a portion of a store request address.

Abstract: The present invention provides a circuit for generating a programmable write-read word line equality signal in FIFO buffers. The present invention significantly reduces the gate delay associated in producing the write-read word line equality signal. The delay is reduced from a typical 30-50 gate delays, to as little as four gate delays. The present invention accomplishes this by processing several bit operations in parallel and making the general circuit architecture symmetric. The delay is constant in all of the parallel paths but amounts to only a short delay for the final WREQ output.

Abstract: An instruction scanning unit for a superscalar microprocessor is disclosed. The instruction scanning unit processes start, end, and functional byte information (or predecode data) associated with a plurality of contiguous instruction bytes. The processing of start byte information and end byte information is performed independently and in parallel, and the instruction scanning unit produces a plurality of scan values which identify valid instructions within the plurality of contiguous instruction bytes. Additionally, the instruction scanning unit is scaleable. Multiple instruction scanning units may be operated in parallel to process a larger plurality of contiguous instruction bytes. Furthermore, the instruction scanning unit detects error conditions in the predecode data in parallel with scanning to locate instructions. Moreover, in parallel with the error checking and scanning to locate instructions, MROM instructions are located for dispatch to an MROM unit.

Abstract: A method and apparatus for executing floating point and packed data instructions using a single physical register file that is aliased. According to one aspect of the invention, a processor is provided that includes a decode unit, a mapping unit, and a storage unit. The decode unit is configured to decode instructions and their operands from at least one instruction set including at least a first and second set of instructions. The storage unit includes a physical register file. The mapping unit is configured to map operands used by the first set of instructions to the physical register file in a stack referenced manner. In addition, the mapping unit is configured to map operands used by the second set of instructions to the same physical register file in a non-stack reference manner.