Abstract: Examples of circuitry and systems and methods provide a multi-way configurable amplifier to support various applications. The multi-way configurable amplifier may include a reconfigurable filter that comprises first and second inputs adapted to receive an input signal; a fully differential amplifier (FDA); and first and second reconfigurable resistance-capacitance (RC) networks. The FDA has an inverting input, a non-inverting input, an inverting output, and a non-inverting output. The inverting input is coupled to the first input, and the non-inverting input is coupled to the second input. The first reconfigurable RC network is coupled to the non-inverting output, and the second reconfigurable RC network is selectively couplable to the inverting output. The reconfigurable filter is configurable to enable operation in any of multiple modes including a single-ended mode of operation and a differential mode of operation.

Abstract: Systems and apparatuses are disclosed that include a distributed power system configured to provide power to a number of loads. The system includes power converters configured to receive DC power from a common power source, each of the plurality of power converters configured to provide DC power to a corresponding load from. Each of the power converters is positioned proximal to the corresponding load that it powers.

Abstract: A power amplifier system having a carrier amplifier having a first supply node, a peaking amplifier having a second supply node, and envelope tracking (ET) circuitry is disclosed. The ET circuitry has a first tracking amplifier that generates a first voltage signal at the first supply node, a second tracking amplifier that generates a second voltage signal at the second supply node, and a transistor coupled between the first supply node and the second supply node. A control circuit has a first input coupled to an output of both or either of the first tracking amplifier and the second tracking amplifier and a control output terminal coupled to a control input terminal of the transistor, wherein the control circuit is configured to progressively turn on the transistor to pass current from the first supply node to the second supply node as the peaking amplifier progressively becomes active.

Abstract: An improved audio amplifier system can both reduce power consumption by supporting a standby mode and shorten wake time when resuming from the standby mode. The audio amplifier system may reduce power by entering a sleep or standby state in response to a command and/or detecting that an audio input signal is not received. Further, the audio amplifier system may use a burst generator to periodically or intermittently activate the power supply during standby mode. By periodically or intermittently activating the power supply, one or more of the capacitors may be charged. By charging the capacitors during standby mode, the time to wake from standby mode may be significantly reduced. In some cases, the wake time may be reduced by several order of magnitudes (e.g., from seconds to milliseconds).

Abstract: A peak detector for a power amplifier is provided that includes a threshold voltage detector configured to pulse a detection current in response to an amplified output signal from the amplifier exceeding a peak threshold. A plurality of such peak detectors may be integrated with a corresponding plurality of power amplifiers in a transmitter. Should any peak detector assert an alarm signal or more than a threshold number of alarm signals during a given period, a controller reduces a gain for the plurality of power amplifiers.

Abstract: A wide band matching network for power amplifier impedance matching, the wide band matching network comprising: a power amplifier transistor connected to an output network; the output network including: a series capacitor; an on-chip transformer connected to the capacitor in series, wherein the transformer and the capacitor act as a second order filter; and a port connected to the capacitor and a receiver switch.

Abstract: Bias circuits and methods for silicon-based amplifier architectures that are tolerant of supply and bias voltage variations, bias current variations, and transistor stack height, and compensate for poor output resistance characteristics. Embodiments include power amplifiers and low-noise amplifiers that utilize a cascode reference circuit to bias the final stages of a cascode amplifier under the control of a closed loop bias control circuit. The closed loop bias control circuit ensures that the current in the cascode reference circuit is approximately equal to a selected multiple of a known current value by adjusting the gate bias voltage to the final stage of the cascode amplifier. The final current through the cascode amplifier is a multiple of the current in the cascode reference circuit, based on a device scaling factor representing the relative sizes of the transistor devices in the cascode amplifier and in the cascode reference circuit.

Abstract: An amplifier for converting a differential input signal to a single ended output signal. In particular, the amplifier including a converting circuit for converting a differential input signal into a single ended output signal, the converting circuit including an input section for receiving the differential input signal and an output section including an output port for providing the single ended output signal, where the output section includes a capacitive element configured to reduce an intrinsic time constant of the converting circuit.

Abstract: Methods and devices to improve nonlinearity performance of low noise amplifiers (LNAs) are disclosed. The described methods and devices reduce the capacitive loading of the LNA amplifying devices on the bypass path of the LNAs when operating in the bypass mode. This is performed by decoupling the active devices from ground to put the amplifying devices in a floating state, thus minimizing the impact of the gate-source capacitances of the amplifying devices on the overall linear performance of the LNA operating in the bypass mode.

Abstract: According to one embodiment, a signal processing circuit includes a first voltage setting circuit that sets a reference voltage on an input side of an isolator, a variable gain amplifier circuit that amplifies an output signal of the isolator, a DC offset adjustment circuit that adjusts an offset of the variable gain amplifier circuit, a second voltage setting circuit that sets a reference voltage on an output side of the isolator, and a control circuit that controls the DC offset adjustment circuit in response to a result of comparison of an output voltage of the variable gain amplifier circuit with an output voltage of the second voltage setting circuit.

Abstract: Described herein is a reconfigurable asymmetrical load-modulated balanced amplifier. The reconfigurable asymmetrical load-modulated balanced amplifier can include a radio frequency (RF) input port, an RF output port, a peaking amplifier circuit operably coupled between the RF input and RF output ports, where the peaking amplifier circuit is a balanced amplifier that comprises a pair of asymmetrical power amplifiers, and a carrier amplifier circuit operably coupled to the RF input port.

Abstract: A lookup table calibration apparatus and method are disclosed. The lookup table calibration apparatus includes a power amplifier circuit configured to amplify a radio frequency (RF) signal having time-variant power levels based on a modulated voltage. To ensure proper alignment between the modulated voltage and the time-variant power levels, the power amplifier circuit is further configured to phase-shift the RF signal based on a modulated phase correction voltage. Specifically, the modulated voltage is generated based on a modulated voltage lookup table and the modulated phase correction voltage is generated based on a phase correction voltage lookup table. Herein, the lookup table calibration apparatus can be configured to concurrently populate and/or calibrate the modulated voltage lookup table and the phase correction voltage lookup table based on a measured gain and a measured phase of the RF signal, respectively.

Abstract: An amplifier may include multiple transistors with two transistors having their gates tied together via a common connection. The amplifier may utilize a local common mode feedback resistor as part of the amplifier. The local common mode feedback resistor may be coupled between the common connection and respective terminals of two transistors of multiple transistors. The local common mode feedback resistor may include a group of resistors coupled in series. The local common mode feedback resistor may also include a metal oxide semiconductor (MOS) resistor coupled in parallel with one or more of the first group of resistors. In the local common mode feedback, the first MOS resistor provides different levels of resistance to different process corners to reduce overshoot when the amplifier is enabled.

Abstract: Target voltage generation in an envelope tracking (ET) integrated circuit (ETIC) is provided. The ETIC is configured to generate a time-variant ET voltage based on a time-variant target voltage for amplifying a radio frequency (RF) signal modulated for communication in multiple time intervals. In embodiments disclosed herein, the ETIC is self-contained to generate the time-variant target voltage based on a sensed signal having a time-variant sensed envelope that tracks a time-variant power envelope of the RF signal. Since the time-variant target voltage is generated to track the time-variant sensed envelope, which further tracks the time-variant power envelope, the time-variant ET voltage can better track the time-variant power envelope of the RF signal when the time-variant ET voltage is provided to a power amplifier(s) that amplifies the RF signal.

Abstract: Systems and methods are provided for amplifying multiple input signals to generate multiple output signals. An example system includes a first channel, a second channel, and a third channel. The first channel is configured to receive one or more first input signals, process information associated with the one or more first input signals and a first ramp signal, and generate one or more first output signals. The second channel is configured to receive one or more second input signals, process information associated with the one or more second input signals and a second ramp signal, and generate one or more second output signals. The first ramp signal corresponds to a first phase. The second ramp signal corresponds to a second phase. The first phase and the second phase are different.

Abstract: An interface circuit includes a first amplifier circuit comprising a first input terminal configured to receive a first input signal, a second input terminal configured to receive a second input signal, a first output node configured to output a first output signal, a second output node configured to output a second output signal, and a variable impedance circuit comprising a first impedance circuit connected to the first output node, and a second impedance circuit connected to the second output node. A code generator circuit is configured to generate a first control code and a second control code. The first impedance circuit is configured to adjust an impedance thereof based on the first control code, and the second impedance circuit is configured to adjust an impedance thereof based on the second control code.

Abstract: This application provides an operational amplifier and a start-up circuit of the operational amplifier. The start-up circuit has the advantages of having a simple structure and consuming less. The operational amplifier includes a multi-stage amplifier and a start-up circuit, where the start-up circuit includes a first start-up transistor and a second start-up transistor. A source of the first start-up transistor and a source of the second start-up transistor are connected to a tail bias node of a first-stage amplifier in the multi-stage amplifier, a gate of the first start-up transistor and a gate of the second start-up transistor are configured to connect to a first bias voltage Vb, and a drain of the first start-up transistor and a drain of the second start-up transistor are connected to input terminals of a second-stage or higher-stage amplifier.

Abstract: A harmonic processing circuit includes: a feeder line configured to feed power to an amplifying device; and a harmonic processing unit connected to the feeder line, and configured to perform harmonic processing to a harmonic of a signal outputted from the amplifying device. The feeder line is connected to a fundamental wave matching circuit that is connected to the amplifying device and performs matching with respect to a fundamental wave of the signal.

Abstract: Voltage ripple suppression in a transmission circuit is disclosed. The transmission circuit includes a power amplifier circuit coupled to an envelope tracking integrated circuit (ETIC) via a conductive path. Notably, the ETIC and the conductive path can present a large source impedance to the power amplifier circuit, which can cause a ripple in the modulated voltage received by the power amplifier circuit. In a conventional approach, the large source impedance may be isolated by a large decoupling capacitor at the expense of increased voltage switching time and battery current drain. In contrast, the ETIC disclosed herein can determine and apply a correction term to the modulated voltage generated by the ETIC to thereby suppress the ripple without requiring the large decoupling capacitor. By eliminating the large decoupling capacitor, the transmission circuit can thus achieve fast voltage switching with lower battery current drain.

Abstract: A delay-compensating power management circuit is provided. The power management circuit includes a power management integrated circuit (PMIC) configured to generate a time-variant voltage(s) based on a time-variant target voltage(s) for amplifying an analog signal(s) associated with a time-variant power envelope(s). A voltage processing circuit is provided in the power management circuit to determine a temporal offset, which can be positive or negative, between the time-variant power envelope(s) and the time-variant target voltage(s). Accordingly, the voltage processing circuit modifies the time-variant target voltage(s) to substantially reduce the determined temporal offset and thereby realign the time-variant target voltage(s) with the time-variant power envelope(s). By realigning the time variant target voltage(s) with the time-variant power envelope(s), it is possible to align the time-variant voltage(s) with the time-variant power envelope(s) to reduce distortions (e.g.