Abstract: An amplifier device includes an amplifier including cascade-connected power amplifiers in a plurality of stages and a bias circuit configured to supply bias currents to the amplifier. A bias current supplied to a power amplifier in the first stage of the power amplifiers in the plurality of stages exhibits a positive temperature characteristic. A bias current supplied to a power amplifier in the final stage exhibits a negative temperature characteristic.

Abstract: Bias circuits and methods for silicon-based amplifier architectures that are tolerant of supply and bias voltage variations, bias current variations, and transistor stack height, and compensate for poor output resistance characteristics. Embodiments include power amplifiers and low-noise amplifiers that utilize a cascode reference circuit to bias the final stages of a cascode amplifier under the control of a closed loop bias control circuit. The closed loop bias control circuit ensures that the current in the cascode reference circuit is approximately equal to a selected multiple of a known current value by adjusting the gate bias voltage to the final stage of the cascode amplifier. The final current through the cascode amplifier is a multiple of the current in the cascode reference circuit, based on a device scaling factor representing the relative sizes of the transistor devices in the cascode amplifier and in the cascode reference circuit.

Abstract: A first embodiment is directed to a circuit including a positive biasing circuit with a drive PMOS for biasing in subthreshold, a negative biasing circuit with a drive NMOS for biasing in subthreshold, and an amplification circuit coupled to the biasing circuits. The amplification circuit includes a first stage with a first boosting stage, a second stage with a second boosting stage, and a resistive element coupled between the first and second stages. A second embodiment is directed to a folded cascode operational amplifier wherein a value of the resistive element is selected to place at least one of a drive MOS in subthreshold. A third embodiment is directed to an integrated circuit with a resistive area neighboring a first boosting area and a second boosting area, the resistive area including a resistive element directly connected to a drive PMOS and a drive NMOS.

Abstract: An apparatus comprising a first circuit and a circuit. The first circuit may be configured to receive an input signal, split the input signal into component signals and present the component signals to a plurality of amplifiers. The second circuit may be configured to receive amplified component signals from the amplifiers and combine the amplified component signals into an output signal. The circuits may each comprise an outer conductor, an inner conductor, a cavity and a plurality of blades. Each of the blades may be arranged evenly spaced along a surface within the cavity and extend along a length of the surface with a shape. The shape of the blades may have a probe and the shape may gradually meet the surface and may be configured to provide a low-loss transition for propagation of a microwave signal. The output signal may be an amplified version of said input signal.

Abstract: A load modulated balanced amplifier (LMBA) circuit can include an input pad of the LMBA circuit configured to receive an input signal on a semiconductor die. A transformer-based hybrid splitter can be coupled to the input pad and configured to provide a first split input signal and a second split input signal from the input signal. A control power amplifier circuit coupled the first split input signal and a power amplifier circuit coupled to the second split input signal.

Abstract: A power amplifier circuit includes a first transistor having a first terminal to which a first signal inputs, a second transistor having a first terminal to which the first signal inputs, a first resistor having a first end to which a first bias current is supplied and a second end electrically connected to the first terminal of the first transistor, a second resistor having a first end to which a second bias current is supplied and a second end electrically connected to the first terminal of the second transistor, and a third resistor having a first end connected to the first end of the first resistor and a second end connected to the first end of the second resistor.

Abstract: Envelope tracking power supply circuitry includes a look up table (LUT) configured to provide a target supply voltage based on a power envelope measurement. The target supply voltage is dynamically adjusted based on a delay between the power envelope of an RF signal and a provided envelope tracking supply voltage. The envelope tracking supply voltage is generated from the adjusted target supply voltage in order to synchronize the envelope tracking supply voltage with the power envelope of the RF signal.

Abstract: One example includes a device that is comprised of a pre-power amplifier, a power amplifier, a signal path, and a dynamic bias circuit. The pre-power amplifier amplifies an input signal and outputs a first amplified signal. The power amplifier receives the first amplified signal and amplifies the first amplified signal based on a dynamic bias signal to produce a second amplified signal at an output thereof. The signal path is coupled between an output of the pre-power amplifier and an input of the power amplifier. The dynamic bias circuit monitors the first amplified signal, generates the dynamic bias signal, and outputs the dynamic bias into the signal path.

Abstract: A delay-compensating power management circuit is provided. The power management circuit includes a power management integrated circuit (PMIC) configured to generate a time-variant voltage(s) based on a time-variant target voltage(s) for amplifying an analog signal(s) associated with a time-variant power envelope(s). A voltage processing circuit is provided in the power management circuit to determine a temporal offset, which can be positive or negative, between the time-variant power envelope(s) and the time-variant target voltage(s). Accordingly, the voltage processing circuit modifies the time-variant target voltage(s) to substantially reduce the determined temporal offset and thereby realign the time-variant target voltage(s) with the time-variant power envelope(s). By realigning the time variant target voltage(s) with the time-variant power envelope(s), it is possible to align the time-variant voltage(s) with the time-variant power envelope(s) to reduce distortions (e.g.

Abstract: A power amplifier circuit includes a first amplifier that amplifies a first RF signal and outputs a second RF signal, a second amplifier that amplifies the second RF signal and outputs a third RF signal, a bias circuit that supplies a bias current or voltage to the first or second amplifier, and a bias adjustment circuit that adjusts the bias current or voltage on the basis of the first RF signal, the second RF signal, or the third RF signal. The bias adjustment circuit includes a first diode having an anode to which a control signal indicating a signal based on the first, second, or third RF signal is inputted, and a cathode connected to a ground. The bias circuit includes a bias transistor that outputs the bias current or voltage on the basis of a voltage at the anode of the first diode.

Abstract: A power management circuit operable to reduce rush current is provided. The power management circuit is configured to provide a time-variant voltage(s) to a power amplifier(s) for amplifying a radio frequency (RF) signal(s). Notably, a variation in the time-variant voltage(s) can cause a rush current that is proportionally related to the variation of the time-variant voltage(s). To reduce the rush current, the power management circuit is configured to maintain the time-variant voltage(s) at a non-zero standby voltage level when the power amplifier(s) is inactive. When the power amplifier(s) becomes active and the time-variant voltage(s) needs to be raised or reduced from the non-zero standby voltage level, the rush current will be smaller as a result of reduced variation in the time-variant voltage(s). As such, it is possible to prolong the battery life in a device employing the power management circuit.

Abstract: A differential input stage of a circuit includes a first transistor, a second transistor, a third transistor, and a fourth transistor. Drains of the first and third transistors couple together at a first node, and drains of the second and fourth transistors couple together at a second node. A first slew boost circuit includes a fifth transistor and a first current mirror. A gate of the fifth transistor couples to the second node. A source of the fifth transistor couples to the first node. The first current mirror couples to the fifth transistor and to the second node. A second slew boost circuit includes a sixth transistor and a second current mirror. A gate of the sixth transistor couples to the first node. A source of the sixth transistor couples to the second node. The second current mirror couples to the sixth transistor and to the first node.

Abstract: A circuit arrangement, including: a circuit configured to synthesize a resistor having a resistance value having a variation in time equivalent to a resistance variation of a sensor resistor applied with a resistance bias voltage and a resistance current bias, wherein the circuit includes: an amplifier comprising an input transistor; a bias current generator comprising a control node coupled to an output of the input transistor, wherein the bias current generator is configured to generate a bias current flowing in the input transistor; and a further current generator configured to generate a current at least proportional to the resistance bias current and coupled to the output of the input transistor, wherein the resistance bias voltage is applied to an input of the amplifier, and wherein a transconductance of the input transistor is at least proportional to the resistance of the sensor resistor.

Abstract: Disclosed is a system that comprises an operational amplifier with adjustable operational parameters and a trimming module. The trimming module can adjust the operational parameters of the op-amp based on a memory value to compensate for an offset voltage of the op-amp. The trimming module can comprise successive approximation register (SAR) logic that controls the memory value. The SAR logic can be configured to detect a given memory value that causes an output voltage of the op-amp to be within a predetermined voltage interval when applying a predetermined common mode voltage to inverting and non-inverting inputs of the op-amp.

Abstract: Disclosed are systems, devices, modules, methods, and other implementations, including a method for digital predistortion that includes receiving, by a digital predistorter, a first signal that depends on amplitude variations based on an input signal, u, with the variations of the first signal corresponding to time variations in non-linear characteristics of a transmit chain that includes a power amplifier. The method further includes receiving, by the digital predistorter, the input signal u, generating, by the digital predistorter, based at least in part on signals comprising the input signal u and the first signal, a digitally predistorted signal v to mitigate the non-linear behavior of the transmit chain, and providing the predistorted signal v to the transmit chain.

Abstract: Disclosed is a phase shifter, which includes a signal generator that generates a first signal and a second signal having a phase orthogonal to a phase of the first signal, and outputs the first signal and the second signal, an operator that generates a first current and a second current, and amplifies the first current and the second current, and a signal converter converting a first digital signal and a second digital signal. The operator includes an input circuit converting the first signal and the second signal, a path selection circuit determining paths of the generated first current and the generated second current, and a cascode circuit buffering the first current and the second current. The operator sums the first current and the second current, controls a vector of the first current and a vector of the second current, and generates a voltage signal through an output load.

Abstract: an electronic circuit according to an embodiment includes: a generation circuit generating a first clocksignal and a second clocksignal delayed from the first clocksignal; a first coupler transmitting one of the first and the second clocksignals by electromagnetic coupling; a first converter driven by the transmitted clocksignal and converting a first input signal into a first signal of a frequency corresponding to the transmitted clocksignal; a second coupler transmitting the first signal by electromagnetic coupling; a second converter converting the first signal into a second signal of a frequency corresponding to the first input signal with the other of the first and the second clocksignals; an output device outputting the second signal; and a protection circuit connected to a line through which the one of the first and the second clocksignals is transmitted between the first coupler and the first converter.

Abstract: An autotuning controller is provided for improving power efficiency and linearity of digital power amplifiers (DPAs). The controller includes an interface including input and output terminals connected to the DPAs, the interface being configured to acquire input signals and output signals, a digital pre-distortion (DPD)-DPA adaptive controller including a processor and a memory running and storing a DPD algorithm, an efficiency enhancement method and a learning cost function.

Abstract: An amplifier module includes a module substrate with a mounting surface, a signal conducting layer, a ground layer, and a ground terminal pad at the mounting surface. A thermal dissipation structure extends through the module substrate. A ground contact of a power transistor die is coupled to a surface of the thermal dissipation structure. Encapsulant material covers the mounting surface of the module substrate and the power transistor die, and a surface of the encapsulant material defines a contact surface of the amplifier module. A ground terminal is embedded within the encapsulant material. The ground terminal has a proximal end coupled to the ground terminal pad, and a distal end exposed at the contact surface. The ground terminal is electrically coupled to the ground contact of the power transistor die through the ground terminal pad, the ground layer of the module substrate, and the thermal dissipation structure.

Abstract: In accordance with an embodiment, a method for operating a millimeter-wave power amplifier including an input transistor having an output node coupled to a load path of a cascode transistor includes: receiving a millimeter-wave transmit signal at a control node of the input transistor; amplifying the millimeter-wave transmit signal to form an output signal; providing the output signal to a load coupled to an output node of the cascode transistor; and adjusting a first DC bias current of the input transistor to form a substantially constant second DC bias current of the cascode transistor.