Patents Examined by Patrick C Chen
  • Patent number: 10860044
    Abstract: Apparatuses and methods relating generally to reduction of allocation of external power and/or ground pins of a microelectronic device are disclosed. In one such apparatus, an external power input pin is configured for receiving an input supply-side power having an external supply voltage level higher than an internal supply voltage level and an external supply current level lower than an internal supply current level. An internal power plane circuit coupled to the external power input pin is configured to step-down a voltage from the external supply voltage level to the internal supply voltage level and to step-up a current from the external supply current level to the internal supply current level to provide an internal power source.
    Type: Grant
    Filed: December 13, 2016
    Date of Patent: December 8, 2020
    Assignee: XILINX, INC.
    Inventor: Stephen M. Trimberger
  • Patent number: 10855294
    Abstract: A high linearity phase interpolator (PI) is disclosed. A phase value parameter indicative of a desired phase difference between an output signal and an input clock signal edge may be provided by control logic. A first capacitor may be charged for a first period of time with a first current that is proportional to the phase value parameter to produce a first voltage on the capacitor that is proportional to the phase value parameter. The first capacitor may be further charged for a second period of time with a second current that has a constant value to form a voltage ramp offset by the first voltage. A reference voltage may be compared to the voltage ramp during the second period of time. The output signal may be asserted at a time when the voltage ramp equals the reference voltage.
    Type: Grant
    Filed: November 8, 2016
    Date of Patent: December 1, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Baher Haroun, Wenting Zhou, Kai Yiu Tam, Reza Hoshyar, Ali Kiaei
  • Patent number: 10826386
    Abstract: A multi-stage charge pump including a first stage configured to generate a first output voltage, a last stage configured to receive the first output voltage from the first stage and output a second output voltage, a switch configured to receive the second output voltage from the last stage, and a voltage regulator circuit configured to control the second output voltage of the last stage to maintain a substantially constant on-resistance of the switch.
    Type: Grant
    Filed: October 26, 2018
    Date of Patent: November 3, 2020
    Assignee: NXP B.V.
    Inventors: Xiaoqun Liu, Madan Mohan Reddy Vemula
  • Patent number: 10797693
    Abstract: A drive circuit includes: a control circuit providing control voltage to a control terminal of a switching device in accordance with input signal; and a capacitor having one end connected to a high side main terminal of the switching device, wherein the control circuit increases an output current capacity of the control circuit when the input signal becomes ON signal and voltage at the other end of the capacitor drops.
    Type: Grant
    Filed: October 26, 2018
    Date of Patent: October 6, 2020
    Assignee: Mitsubishi Electric Corporation
    Inventor: Hiroshi Yoshida
  • Patent number: 10797585
    Abstract: A controller controls Pulse Width Modulation (PWM) signals of one or more phases. The controller includes a phase sequencer to select a phase, a common ramp generator generating a common ramp signal, a phase activation circuit to turn on the PWM signal of the selected phase based on the common ramp signal, and for each phase a Current Sense plus Ramp (CSR) signal generator to generate a phase CSR signal according to a current of the phase and a phase deactivation circuit to turn off the PWM signal of the phase based on the phase CSR signal. A method of controlling PWM phases comprises selecting a phase, generating a common ramp signal, turning on the PWM signal of the selected phase based on the common ramp signal, generating CSR signals according to currents of the phases, and turning off the PWM signals based on the respective CSR signals.
    Type: Grant
    Filed: February 14, 2019
    Date of Patent: October 6, 2020
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Gang Chen, Gabor Reizik
  • Patent number: 10790839
    Abstract: Device for adjusting the locking of an injection locked frequency multiplier, including: a first input receiving a first signal of frequency f1, and a second input receiving a second signal of frequency f2 outputted by the frequency multiplier; a sub-sampler of the second signal; a control circuit configured for: receiving a third signal corresponding to the second signal sub-sampled by the first signal or by another multiple signal of frequency of f1, then carrying out a high-pass or band-pass filtering of the third signal; determining that the frequency multiplier is locked on a multiple of f1 when the signal obtained after filtering is substantially zero, then outputting a signal the value of which is representative of the locking or not of the frequency multiplier.
    Type: Grant
    Filed: September 13, 2019
    Date of Patent: September 29, 2020
    Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Clement Jany, Jose-Luis Gonzalez Jimenez, Frederic Hameau, Alexandre Siligaris
  • Patent number: 10790835
    Abstract: A system for phase control of a Phased Locked Loop, PLL, is disclosed. The system includes the PLL. The PLL includes an oscillator configured to generate an output signal; a frequency divider configured to generate a feedback signal by dividing the output signal from the oscillator; a first phase detector arrangement configured to output a first control signal to control the oscillator in response to a detection of a phase deviation between a reference signal and the feedback signal. A second phase detector is configured to receive the feedback signal from the frequency divider and the reference signal, and generate an output signal. A phase calibration circuit is configured to receive the output signal from the second phase detector and generate a second control signal to adjust a phase of the output signal of the oscillator.
    Type: Grant
    Filed: March 1, 2017
    Date of Patent: September 29, 2020
    Assignee: Telefonaktiebolaget LM Ericsson (Publ)
    Inventors: Staffan Ek, Tony Påhlsson, Henrik Sjöland
  • Patent number: 10778231
    Abstract: A clock dividing frequency circuit can include: a controlled current source configured to generate a driving current that varies with a dividing frequency control signal; a ramp signal generating circuit configured to generate a ramp signal having a slope that varies according to the driving current, where the ramp signal is reset according to pulses of a dividing frequency clock signal; and a dividing frequency pulse generating circuit configured to generate the dividing frequency clock signal by a dividing frequency operation according to the ramp signal and a system clock signal.
    Type: Grant
    Filed: December 1, 2017
    Date of Patent: September 15, 2020
    Assignee: Silergy Semiconductor Technology (Hangzhou) LTD
    Inventors: Jaime Tseng, Xiaoping Chen, Hongfeng Fan
  • Patent number: 10763851
    Abstract: A gate control circuit has a first gate controller that controls a gate voltage of a first transistor connected between a first reference voltage node and an output node on the basis of a potential difference between the first reference voltage node and a second reference voltage node, a second gate controller that controls a gate voltage of a second transistor connected between the output node and a fourth reference voltage node. and a voltage adjustment circuit that temporarily increases the potential difference between the first reference voltage node and the second reference voltage node in a first period in which the voltage of the first reference voltage node is rising from an initial voltage and a second period in which the voltage of the first reference voltage node is falling from a normal voltage.
    Type: Grant
    Filed: September 3, 2019
    Date of Patent: September 1, 2020
    Assignees: Kabushiki Kaisha Toshiba, Toshiba Electronic Devices & Storage Corporation
    Inventor: Yukio Tsunetsugu
  • Patent number: 10756723
    Abstract: A semiconductor apparatus includes first and second edge detection signal generators. The first edge detection signal generator may generate a first edge detection signal by gating an input signal and its inverted signal based on a first gating control signal, generated by delaying the input signal, and output the first edge detection signal to an output node. The second edge detection signal generator may generate a second edge detection signal by gating a complementary signal of the input signal and its inverted signal based on a second gating control signal, generated by delaying the complementary signal, and output the second edge detection signal to the output node. An output signal may be generated at the output node.
    Type: Grant
    Filed: June 8, 2018
    Date of Patent: August 25, 2020
    Assignee: SK hynix Inc.
    Inventor: Dong Hyun Kim
  • Patent number: 10749479
    Abstract: System and method for integrating an input signal to generate an output signal. The system includes a first integrator configured to receive the input signal and generate an integrated signal based on at least information associated with the input signal, a second integrator configured to receive the integrated signal and generate the output signal based on at least information associated with the integrated signal, and a compensation capacitor coupled to the first integrator and the second integrator. The first integrator includes a first integration capacitor and a first operational amplifier including a first input terminal and a first output terminal, the first integration capacitor being coupled between the first input terminal and the first output terminal. The second integrator includes a second integration capacitor and a second operational amplifier including a second input terminal and a second output terminal.
    Type: Grant
    Filed: January 13, 2015
    Date of Patent: August 18, 2020
    Assignee: On-Bright Electronics (Shanghai) Co., Ltd.
    Inventors: Tingzhi Yuan, Yunchao Zhang, Zhiqiang Sun, Lieyi Fang
  • Patent number: 10749473
    Abstract: An apparatus for performing a frequency multiplication of an mm-wave wave signal is provided. The apparatus includes a first differential circuit that is capable of receiving a 0° phase component of an input signal and a 180° phase component of the input signal having a first frequency. The first differential circuit provides a first output signal that is twice the frequency and is in ?phase(0°) based on the 0° the 180° phase components of the input signal. The apparatus also includes a second differential circuit that is capable of receiving a 90° phase component of the input signal and a 270° phase component of the input signal, and provide a first output signal that is twice the frequency and out of phase(180°). The apparatus also includes a differential transformer that is configured to receive the first output signal and the second output signal. The differential transformer is configured to provide a differential output signal that has a second frequency that is twice the first frequency.
    Type: Grant
    Filed: April 30, 2018
    Date of Patent: August 18, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Abdellatif Bellaouar, Arul Balasubramaniyan
  • Patent number: 10742059
    Abstract: A power management system for dispensers is described. The system includes a controller connected to a lower power zero net voltage (ZNV) power source. A power rectification circuit (PRC) converts ZNV power to higher voltage direct current (HVDC) power. An energy storage system connected to the HVDC power source receives and stores HVDC power within the energy storage system which is selectively provided to a dispenser motor load connected to the energy storage system. The system provides an effective solution to the problem of transferring power from a low power battery source on a disposable product to a dispenser as well as providing a system that minimizes corrosion at the electrical interface between the disposable product and the dispenser particularly in higher humidity environments.
    Type: Grant
    Filed: July 20, 2018
    Date of Patent: August 11, 2020
    Assignee: Smart Wave Technologies, Inc.
    Inventors: Peter Zosimadis, Paul Waterhouse
  • Patent number: 10734993
    Abstract: The optimal operating voltage of a complex SoC may be influenced by process variations. The operating voltages may be dynamically adjusted for optimal performance. These adjustments require a dynamic reconfiguration of the voltage monitoring thresholds in the power on reset circuitry of the SoC.
    Type: Grant
    Filed: December 29, 2016
    Date of Patent: August 4, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Venkateswar Reddy Kowkutla, Chunhua Hu, Erkan Bilhan, Sumant Dinkar Kale
  • Patent number: 10725489
    Abstract: A semiconductor device including a resistance section that includes a first terminal and a second terminal disposed in contact with an outer periphery, and a serial resistance section in which plural resistance elements are connected in series, wherein one end of the serial resistance section is connected to the first terminal, and another end of the serial resistance section is connected to the second terminal; and a current adjustment section that includes a current source that supplies current to the serial resistance section, and disposed adjacent to the resistance section such that a distance between the first terminal and the current adjustment section along the outer periphery of the resistance section and a distance between the second terminal and the current adjustment section along the outer periphery of the resistance section are equal.
    Type: Grant
    Filed: January 13, 2017
    Date of Patent: July 28, 2020
    Assignee: LAPIS SEMICONDUCTOR CO., LTD.
    Inventor: Hiroyuki Kikuta
  • Patent number: 10714155
    Abstract: A charge pump circuit includes a voltage input port, a voltage output port, a plurality of charge pump units cascaded between the voltage input port and the voltage output port, a clock signal source, and N clock delay elements. The clock signal source generates a main clock signal and the N clock delay elements generate clock signals received by the charge pump units by delaying the main clock signal. The main clock signal received by the first charge pump unit has a rising edge leading a rising edge of the last clock signal received by the last charge pump unit, and a falling edge lagging the rising edge of the last clock signal. Each of the charge pump units includes two sets of inverters with delay elements for generating two complementary clock signals.
    Type: Grant
    Filed: January 15, 2019
    Date of Patent: July 14, 2020
    Assignee: eMemory Technology Inc.
    Inventors: Wu-Chang Chang, Cheng-Te Yang
  • Patent number: 10715131
    Abstract: A switching power device (100) is provided which comprises: a normally-ON transistor (12), a normally-OFF metal-oxide-semiconductor field-effect transistor (MOSFET) (14), the normally-OFF MOSFET (14) being connected in series to a source terminal (12S) of the normally-ON transistor (12), and a driver (16) connected to and arranged to drive a gate terminal (12G) of the normally-ON transistor (12). A switching transistor (28) can then be positioned between the source terminal (12S) of the normally-ON transistor (12) and a common connection (30) of the driver (16) to protect the switching power device (100) from deleterious over-voltage and over-current spikes.
    Type: Grant
    Filed: April 11, 2016
    Date of Patent: July 14, 2020
    Assignee: Visic Technologies Ltd
    Inventors: Gregory Bunin, David Shapiro
  • Patent number: 10715125
    Abstract: A circuit and a method for detecting a current zero-crossing point, and a circuit and method for detecting a load voltage are disclosed. The circuit for detecting current zero-crossing point includes: a load power supply circuit, a voltage-dividing resistor, a transistor switch, a zero-crossing detection circuit; the load power supply circuit includes: a load, a diode, and a transformer; one end of a primary winding of the transformer is connected with the operating voltage input terminal, the other end of the primary winding of the transformer is connected with a first end of the transistor switch and a first end of the voltage-dividing resistor, a second end of the voltage-dividing resistor and a second end of the transistor switch are connected with the ground, the load voltage is controlled by the transistor switch.
    Type: Grant
    Filed: July 30, 2019
    Date of Patent: July 14, 2020
    Assignee: JOULWATT TECHNOLOGY (HANGZHOU) CO., LTD
    Inventors: Pitleong Wong, Yang Lu, Yue Ji, Yuancheng Ren, Xunwei Zhou
  • Patent number: 10715135
    Abstract: A gate driver circuit comprises a sensor, an amplifier, a regulator and a gate driver. The sensor is configured to sense a collector-emitter voltage and includes a first resistor and a second resistor connected in series, a high voltage diode connected between the series connected first and second resistors and a first capacitor connected parallel to the second resistor. The amplifier is configured to amplify a sensor output voltage and includes a non-inverting operational amplifier controlled by means of a plurality of resistors, a voltage follower connected to an output terminal of the non-inverting operational amplifier through a first diode and a third resistor connected across the first diode and the voltage follower. The regulator is configured to regulate a regulator output voltage based on an amplifier voltage. The gate driver is configured to connect/disconnect the regulator output voltage to the base terminal of the BJT.
    Type: Grant
    Filed: May 29, 2018
    Date of Patent: July 14, 2020
    Assignee: Software Motor Company
    Inventors: Alejandro Pozo Arribas, Mahesh Krishnamurthy
  • Patent number: 10707867
    Abstract: A driver includes an open drain output transistor, a capacitor, a first current source, and first and second transistors. Upon assertion of a transmit signal to turn on the first transistor, a controller asserts a second control signal to turn on the second transistor responsive to a voltage of the capacitor being less than a threshold voltage of the open drain output transistor to thereby increase the gate voltage for the open drain output transistor at a first time rate. The controller deasserts the second control signal to turn off the second transistor responsive to the capacitor voltage exceeding the threshold voltage. Responsive to the capacitor's voltage exceeding the threshold, the first current source charges the capacitor to further increase the gate voltage at a second time rate that is smaller than the first time rate.
    Type: Grant
    Filed: December 7, 2017
    Date of Patent: July 7, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Deep Banerjee, Lokesh Kumar Gupta, Somshubhra Paul