Patents Examined by Patrick C Chen
  • Patent number: 10700668
    Abstract: The present disclosure provides a pulse generator which generates a pulse train by mixing pulses of a first clock having a first frequency, with pulses of a second clock having a second frequency. Over a predefined time period, the combination of pulses results in a pulse train having an effective frequency which is between the first and second frequencies. A multiplexer is used to select which of the first and second clocks should be provided to the output. Depending on the desired target frequency, the multiplexer is controlled to mix differing amounts of pulses from the first and second clocks. A multiplexer is controlled by a control signal, which is generated using combinatorial logic using the first clock as an input. The pulse generator may be used, for example, as a clock for a charge pump.
    Type: Grant
    Filed: June 15, 2018
    Date of Patent: June 30, 2020
    Assignee: Analog Devices Global Unlimited Company
    Inventors: David Sayago, Thomas F. Roche, John A. Cleary
  • Patent number: 10686406
    Abstract: A circuit comprising: a first passive mixer (21) having mixer inputs configured to receive in-phase (I) and quadrature-phase (Q) differential signals; and a first differential sub-circuit (31). The first passive mixer is configured to switch the in-phase (I) and quadrature-phase (Q) differential signals to the first differential sub-circuit at a mixing frequency. The first differential sub-circuit (31) has a pair of differential inputs configured to receive the switched in-phase (I) and quadrature-phase (Q) differential signals from the first passive mixer (21), each input having a capacitance capable of storing a charge that depends on the switched in-phase or quadrature-phase signals. The circuit further comprises a charge canceller configured to supply, to at least one of: the mixer inputs; and the pair of differential inputs, an opposite charge compared with a charge that has been stored on the pair of differential inputs by the operation of the first passive mixer.
    Type: Grant
    Filed: April 24, 2015
    Date of Patent: June 16, 2020
    Assignee: u-blox AG
    Inventor: Niall Duncan
  • Patent number: 10673417
    Abstract: Spectrally-efficient digital logic (SEDL) techniques implement spectrally-efficient pulses (e.g., Gaussian-shaped pulses) in lieu of conventional square waveforms to improve electromagnetic, radio frequency, and other unwanted emissions. The SEDL techniques can be used for combinatorial or sequential logic elements and circuits. A SEDL circuit includes a multiplier circuit configured to receive a clock signal and provide a product of the input signal and a clock signal, an integrator circuit to integrate the product signal over a first portion of a clock period to determine the logic state of the input signal, a limit circuit configured to apply limits to a state result provided to the integrator circuit, and a pulse generator configured to receive the logic state from the limit circuit and provide and output signal having a Gaussian-shaped output pulse that represents that logic value corresponding to the logic value of the input signal.
    Type: Grant
    Filed: June 27, 2018
    Date of Patent: June 2, 2020
    Assignee: Massachusetts Institute of Technology
    Inventor: Robert J. Murphy
  • Patent number: 10666269
    Abstract: An apparatus comprising an accumulator circuit and an offset register. The accumulator circuit may be configured to (a) receive a plurality of frequency offset values from a plurality of sourcing DPLLs and (b) generate a current combined offset value in response to a sum of the frequency offset values. The offset register may be configured to (a) store an offset value corresponding to the current combined offset value in a first mode and (b) store an offset value corresponding to an updated offset value in a second mode. The updated offset value may comprise a difference between the offset value stored in the offset register and the current combined offset value. The offset value may be presented to a receiving DPLL during a re-arrangement of the sourcing DPLLs. Presenting the offset value may reduce a phase transient caused by the re-arrangement.
    Type: Grant
    Filed: June 25, 2019
    Date of Patent: May 26, 2020
    Assignee: Integrated Device Technology, Inc.
    Inventor: Menno Spijker
  • Patent number: 10651732
    Abstract: Methods of operating a charge pump, and charge pumps configured to perform similar methods, involve monitoring a level of a supply voltage of the charge pump, and turning off an oscillator of the charge pump responsive to the level of the supply voltage dropping below a certain level, wherein turning off the oscillator comprises setting an inverter in a ring oscillator loop of the oscillator to a steady state output.
    Type: Grant
    Filed: May 16, 2019
    Date of Patent: May 12, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Ming H. Li, Dong Pan
  • Patent number: 10651857
    Abstract: A phase locked loop system includes bias voltage adjustment circuitry and a voltage regulator that outputs a smoothed core voltage to an oscillator. The bias voltage adjustment circuitry is configured to compute a scaled bias voltage based at least on a target frequency for the oscillator. The voltage regulator is configured to input i) the scaled bias voltage and ii) a selected core voltage that is selected based on the target operating frequency of the oscillator and generate the smoothed core voltage for output to the oscillator.
    Type: Grant
    Filed: June 28, 2016
    Date of Patent: May 12, 2020
    Assignee: Apple Inc.
    Inventors: Andreas Roithmeier, Thomas Gustedt, Herwig Dietl-Steinmaurer, Christian Wicpalek
  • Patent number: 10644699
    Abstract: A circuit includes a first transistor comprising a first control input and first and second current terminals, the first control input coupled to receive a first input control signal, and the first current terminal coupled to a first power supply node. The circuit also includes a first resistor coupled to the first control input of the first transistor, a first capacitor coupled between the second current terminal of the first transistor and the first resistor and a second transistor comprising a second control input and third and fourth current terminals, the third current terminal coupled to the first resistor and to the first capacitor.
    Type: Grant
    Filed: May 31, 2018
    Date of Patent: May 5, 2020
    Inventor: Steven Ernest Finn
  • Patent number: 10637465
    Abstract: In recent years, it has been desired to further shorten the dead time. Provided is a driving device that drives on/off a main switching element to which a free wheeling diode is anti-parallel connected, wherein the driving device includes a determination unit configured to output a determination signal indicating whether free wheeling current is flowing from a source terminal to a drain terminal of the main switching element; and a drive control unit configured to reduce a switching speed when the main switching element is driven from an on-state to an off-state on condition that the determination signal indicating that the free wheeling current is flowing is output.
    Type: Grant
    Filed: June 3, 2019
    Date of Patent: April 28, 2020
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Kunio Matsubara, Tsuyoshi Nagano
  • Patent number: 10637468
    Abstract: An illustrative embodiment of an integrated circuit configured for galvanically isolated signaling includes a transfer conductor carrying a modulated carrier signal. A floating transfer loop is electromagnetically coupled to the transfer conductor to receive the modulated carrier signal. The floating transfer loop includes a primary of a step-up transformer. A receiver is coupled to a secondary of the step-up transformer to receive the modulated carrier signal in an amplified, differential fashion, and to demodulate the modulated carrier signal to obtain a digital receive signal.
    Type: Grant
    Filed: October 23, 2017
    Date of Patent: April 28, 2020
    Inventors: Karel Ptacek, Richard Scott Burton
  • Patent number: 10630287
    Abstract: A radio frequency (RF) device and its voltage generating circuit are provided. The RF device includes the voltage generating circuit and a RF circuit. The voltage generating circuit receives a RF signal and generates at least one bias voltage related to the RF signal. The RF circuit is used to receive the RF signal. The RF circuit is coupled to the voltage generating circuit to receive the bias voltage. The bias voltage is used to operate the conduction state of at least one RF transmission path of the RF circuit.
    Type: Grant
    Filed: October 22, 2018
    Date of Patent: April 21, 2020
    Assignee: RichWave Technology Corp.
    Inventors: Chih-Sheng Chen, Ming-Shiuan Wen
  • Patent number: 10615646
    Abstract: A wireless power transfer system includes a power transmitter (101) arranged to provide a power transfer to a power receiver (105) via a wireless inductive power signal. A parasitic power loss detector (207) is arranged to detect a parasitic power loss for the power transfer, and a user indicator (209) is arranged to initialize a user alert in response to the detection of the parasitic power loss. The system comprises an input (211) for receiving user inputs; and a controller (213) which is arranged to initiate an adaptation of a parasitic power loss detection operation performed by the parasitic power loss detector (207) to detect parasitic power losses if a user input meeting a criterion is not received. Each of the individual features may be implemented in the power transmitter (101), the power receiver (105), or may e.g. be distributed between these. The approach may allow improved foreign object detection in a wireless power transfer system.
    Type: Grant
    Filed: July 15, 2014
    Date of Patent: April 7, 2020
    Assignee: Koninklijke Philips N.V.
    Inventors: Antonius Adriaan Maria Staring, Andries Van Wageningen
  • Patent number: 10601427
    Abstract: A clock generating device includes a divisor register, a reference clock generator, a first counter, a second counter, and a delay regulator circuit. The divisor register provides a divisor. The reference clock generator outputs a reference clock signal. The first counter counts a first number of cycles of the reference clock signal and generates a first count. The first counter outputs a first clock signal according to the first count and the divisor. The second counter counts a second number of cycles of the first clock signal and generates a second count. The second counter outputs a second clock signal according to the second count and a coefficient. The delay regulator circuit determines whether to control the first counter to delay outputting the first clock signal according to the first clock signal.
    Type: Grant
    Filed: July 11, 2019
    Date of Patent: March 24, 2020
    Inventors: Chia-Kuei Hsu, Ming-Kai Chuang, Mei-Chuan Lu
  • Patent number: 10581410
    Abstract: Apparatuses for a flip-flop are provided. One apparatus for a flip-flop includes a domino logic flip-flop, including a single footer transistor for all nodes in the domino logic flip-flop to be pre-charged, wherein the single footer includes a footer node; and a pre-charge transistor connected to the footer node for pre-charging the footer node before an evaluation cycle. Another apparatus for a flip-flop includes a domino logic flip-flop; and combinatory logic configured to evaluate a complimentary signal in conjunction with circuit events.
    Type: Grant
    Filed: February 8, 2016
    Date of Patent: March 3, 2020
    Assignee: Samsung Electronics Co., Ltd
    Inventors: Matthew Berzins, James Jung Lim
  • Patent number: 10573353
    Abstract: Methods of operating a voltage generation circuit include applying a clock signal to an input of a voltage driver of a stage of the voltage generation circuit, connecting the output of the voltage driver to a first voltage node configured to receive a first voltage when the clock signal has a particular logic level and a voltage level of an output of the voltage driver is less than a threshold, connecting the output of the voltage driver to a second voltage node configured to receive a second voltage, greater than the first voltage, when the clock signal has the particular logic level and the voltage level of the output of the voltage driver is greater than the threshold, and connecting the output of the voltage driver to a third voltage node configured to receive a third voltage, less than the first voltage, when the clock signal has a different logic level.
    Type: Grant
    Filed: August 31, 2018
    Date of Patent: February 25, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Agostino Marcerola, Marco-Domenico Tiburzi, Stefano Perugini
  • Patent number: 10574243
    Abstract: An apparatus is provided which comprises: an oscillator to generate a first clock having a first frequency; a divider coupled to the oscillator, wherein the divider is to generate a second clock having a second frequency; and a current reference generator comprising a switched capacitor circuitry which is to receive the second clock directly or indirectly.
    Type: Grant
    Filed: January 24, 2017
    Date of Patent: February 25, 2020
    Assignee: Intel Corporation
    Inventors: Kuan-Yueh Shen, Yongping Fan
  • Patent number: 10566953
    Abstract: An electronic impedance tuner comprises an adjusting circuit, N cell tuning circuits identical in structure and a switch controller. The adjusting circuit comprises a first microstrip line, a second microstrip line, a first capacitor, a second capacitor, a third capacitor, a first inductor, a second inductor and a first PIN diode. Each cell tuning circuit comprises a third microstrip line, a fourth microstrip line, a fourth capacitor, a fifth capacitor, a second PIN diode and a third capacitor. The capacitance Cd of the fourth capacitor meets the condition: 4 ? ? Y s N ? ? ? ? ? f 2 ? ? ? req ? 1 - ? ? req ? 2 ? C d ? Y s ? ? ? f 1 ? ? ? req ? 1 - ? ? req ? 2 . The length d of the third microstrip line meets the condition: ? 1 / 4 ? ( N + 1 ) < d < c 4 ? ? reff ? [ ( C d · Z 0 ) 2 + ( 2 ? ? ? f Bragg ) 2 - C d · Z 0 ] .
    Type: Grant
    Filed: July 7, 2019
    Date of Patent: February 18, 2020
    Assignee: Ningbo University
    Inventors: Ke Wu, Yangping Zhao
  • Patent number: 10559972
    Abstract: Methods, systems, and apparatus, including for back-up power sources. In one aspect, a method includes providing a plurality of first battery devices, each first battery device respectively electrically coupled to a respective server rack in a plurality of server racks and having a respective capacity to provide power to the respective rack for a power anomaly for up to a first duration. Providing a second battery device electrically coupled to the plurality of server racks and having a capacity to provide power to the plurality of respective server racks for a power anomaly for up to a second duration, wherein the second duration is longer than the first duration. A power anomaly is a deviation of mains power from one or more of a nominal supply voltage and frequency.
    Type: Grant
    Filed: April 11, 2018
    Date of Patent: February 11, 2020
    Assignee: Google LLC
    Inventor: Christopher G. Malone
  • Patent number: 10547296
    Abstract: Methods, apparatus, systems, and articles of manufacture are disclosed for cross-conduction detection. An example apparatus includes a cross detector circuit including a first transistor and a second transistor, the first transistor coupled to a load, a third transistor coupled to a first controlled delay circuit and the first transistor, a fourth transistor coupled to a second controlled delay circuit and to the third transistor at a phase node, and a control circuit coupled to the first controlled delay circuit, the second controlled delay circuit, and the load.
    Type: Grant
    Filed: May 30, 2018
    Date of Patent: January 28, 2020
    Assignee: Texas Instruments Incorporated
    Inventors: Gaetano Maria Walter Petrina, Michael Lueders, Nicola Rasera
  • Patent number: 10547290
    Abstract: Systems, methods, and devices are provided to efficiently share an antenna between multiple communication systems and allow for the communication systems to be simultaneously connected to the antenna with less attenuation and/or no fluctuation in signal strength. Communication circuitry may include an antenna that transmits and receives electromagnetic radiation. The communication circuitry may also include an antenna port that provides primary access to the antenna with a first attenuation via an antenna port input. Additionally, the communication circuitry may include a coupler attached to the antenna port. The coupler may provide secondary access to the antenna with a second attenuation.
    Type: Grant
    Filed: September 13, 2017
    Date of Patent: January 28, 2020
    Assignee: Apple Inc.
    Inventors: Chia Yiaw Chong, Mohit Narang, Peter M. Agboh, Hsin-Yuo Liu, Sultan R. Helmi, Tursunjan Yasin, Ye Chen
  • Patent number: 10530360
    Abstract: In accordance with an embodiment, a method includes switching on a transistor device by generating a first conducting channel by driving a first gate electrode and, before generating the first conducting channel, generating a second conducting channel by driving a second gate electrode, wherein the second gate electrode is adjacent the first gate electrode in a current flow direction of the transistor device.
    Type: Grant
    Filed: February 22, 2017
    Date of Patent: January 7, 2020
    Inventors: Markus Bina, Anton Mauder, Jens Barrenscheen