Patents Examined by Patrick C Chen
  • Patent number: 10530358
    Abstract: A switching circuit includes: a main switch array including multiple main switch elements respectively arranged on multiple main signal paths configured in a parallel connection, wherein the multiple main signal paths are coupled with a first circuit node; a main switch control circuit for controlling the multiple main switch elements; an auxiliary switch array including multiple auxiliary switch elements respectively arranged on multiple auxiliary signal paths configured in a parallel connection, wherein the multiple auxiliary signal paths are also coupled with the first circuit node; and an auxiliary switch control circuit for controlling the multiple auxiliary switch elements so as to maintain a total number of turned-on switch elements in the main switch array and the auxiliary switch array to be equal to or more than a threshold quantity.
    Type: Grant
    Filed: June 7, 2018
    Date of Patent: January 7, 2020
    Assignee: REALTEK SEMICONDUCTOR CORP.
    Inventors: Cheng-Pang Chan, Liang-Huan Lei
  • Patent number: 10528071
    Abstract: According to an embodiment of an electronic circuit, the electronic circuit includes a first input pin, a second input pin, an output pin, a control circuit and an output circuit. The first input pin is configured to receive a first input signal that includes an enable information and at least one operation parameter information. The second input pin is configured to receive a second input signal. The control circuit is configured to generate a drive signal based on the enable information included in the first input signal and the second input signal. The output circuit is configured to generate an output signal at the output pin such that a timing of the output signal is dependent on the drive signal and at least one parameter of the output signal is dependent on the at least one operation parameter information included in the first input signal.
    Type: Grant
    Filed: October 14, 2016
    Date of Patent: January 7, 2020
    Assignee: Infineon Technologies Austria AG
    Inventors: Tobias Gerber, Thomas Ferianz
  • Patent number: 10530246
    Abstract: A charge pump circuit is provided, in which a charge pump is supplied with a temperature-dependent bias current, in particular a bias current that decreases with temperature.
    Type: Grant
    Filed: January 18, 2017
    Date of Patent: January 7, 2020
    Assignee: Infineon Technologies AG
    Inventor: Christoph Riedl
  • Patent number: 10528885
    Abstract: A signal generating system is provided. The signal generating system provides a microwave signal to a plurality of qubits. The signal generating system includes a generator, an oscillator, a mixer, and a splitter. The oscillator generates an oscillator signal including a constant frequency. The generator generates a generator signal including an initial frequency. The mixer is electrically coupled to the generator and the oscillator. The mixer combines the generator and oscillator signals to produce the microwave signal. The splitter is electrically coupled to the mixer. The splitter fans-out the microwave signal to a plurality of physical lines. Each of the plurality of physical lines is electrically connected to a corresponding one of the plurality of qubits.
    Type: Grant
    Filed: September 29, 2017
    Date of Patent: January 7, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Jerry M. Chow, Antonio D. Corcoles-Gonzalez, Jay M. Gambetta
  • Patent number: 10516390
    Abstract: A circuit includes an isolator that provides isolated signal communications between a host-side circuit and a converter-side circuit. The isolated signal communications include a conversion start signal generated in the host-side circuit passing through the isolator to become an isolated conversion start signal in the converter-side circuit. The isolated signal communications includes an isolated system clock generated in the converter-side circuit passing through the isolator to become a system clock in the host-side circuit. A sampling clock generator in the host-side circuit generates the conversion start signal based on the system clock. A logic circuit in the converter-side circuit re-clocks the isolated conversion start signal through the logic circuit.
    Type: Grant
    Filed: December 30, 2016
    Date of Patent: December 24, 2019
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Sankar Sadasivam, Anbu Mani, Bryan E. Bloodworth
  • Patent number: 10515669
    Abstract: Voltage generation circuits include a stage including a voltage driver having inputs connected to respective voltage nodes and a clock signal, and a stage capacitance having a first electrode connected to an output of the voltage driver and a second electrode connected to a voltage isolation device. The voltage driver might be configured to connect its output to receive a first voltage when the clock signal has a particular logic level and a voltage level of its output is less than a threshold, to connect its output to receive a second voltage greater than the first voltage when the clock signal has the particular logic level and the voltage level of its output is greater than the threshold, and to connect its output to receive a third voltage less than the first voltage when the clock signal has a different logic level.
    Type: Grant
    Filed: August 31, 2018
    Date of Patent: December 24, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Agostino Macerola, Marco-Domenico Tiburzi, Stefano Perugini
  • Patent number: 10514717
    Abstract: A compensation circuit configured for coupling to a voltage source and a reference circuit. The voltage source is configured for supplying a supply voltage to the compensation circuit and the reference circuit. The reference circuit includes a first circuit node and a reference output electrically coupled to the first circuit node for outputting a reference signal having a constant reference amplitude. The compensation circuit includes a transient converter for converting a first transient perturbation of the supply voltage into a first compensation electrical signal proportional to said first transient perturbation, and an adder coupled to the transient converter for adding the first compensation electrical signal to an electrical signal at the first circuit node with a first polarity opposite to a disturbance polarity of a disturbance of the electrical signal in response to the first transient perturbation.
    Type: Grant
    Filed: January 17, 2017
    Date of Patent: December 24, 2019
    Assignee: NXP USA, Inc.
    Inventors: Olivier Tico, Pascal Kamel Abouda, Yuan Gao
  • Patent number: 10514715
    Abstract: A current control system is disclosed. The current control system may include a controller configured to provide a control signal, an A/D converter dedicated to the controller, a driver configured to supply a current based on the control signal and a sensor configured to provide a digital signal representative of the current to the controller. The digital signal may bypass the dedicated A/D converter. A method for controlling current is likewise disclosed. A circuit for controlling current through an inductive load is likewise disclosed.
    Type: Grant
    Filed: February 24, 2015
    Date of Patent: December 24, 2019
    Assignee: INFINEON TECHNOLOGIES AG
    Inventor: Michael Hausmann
  • Patent number: 10505551
    Abstract: One or more gray code counters, counter arrangements, and phase-locked loop (PLL) circuits are provided. A gray code counter comprises a set of cells, such as standard cells, that output a gray code signal. The gray code counter comprises a pre-ready cell that provides an early signal, generated based upon an early clock, to one or more cells to reduce delay. A counter arrangement comprises one or more counter groups configured to provide pixel count levels for pixels, such as pixels of an image sensor array. A counter group comprises a gray code counter configured to provide a gray code signal to latch counter arrangements of the counter group. A PPL circuit comprises a gray code counter configured to generate a gray code signal used by a digital filter to adjust an oscillator. The gray code signal provides n-bit early/late information to the digital filter for adjustment of the oscillator.
    Type: Grant
    Filed: April 19, 2018
    Date of Patent: December 10, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITED
    Inventor: Chih-Min Liu
  • Patent number: 10476267
    Abstract: A load management system is disclosed. The load management system may include a generator, a power source configured to drive the generator, a load bank configured to produce an electrical load on the generator, a chopper operatively connected to the generator and the load bank, and a chopper regulator in communication with the generator and the chopper. The chopper may be configured to modulate the electrical load of the load bank on the generator. The chopper regulator may be configured to monitor generator parameters and control the chopper based on the generator parameters.
    Type: Grant
    Filed: November 10, 2015
    Date of Patent: November 12, 2019
    Assignee: Caterpillar Inc.
    Inventors: Douglas Brown, Vijay Janardhan, Eric Ohlson
  • Patent number: 10476484
    Abstract: Methods and devices providing Positive Logic biasing schemes for use in a digitally tuning capacitor in an integrated circuit device are described. The described methods can be used in integrated circuits with stringent requirements in terms of switching time, power handling, noise sensitivity and power consumption. The described devices include DC blocking capacitors arranged in series with stacked switches coupled to RF nodes. The stacked FET switches receive non-negative supply voltages through their drains and gates during the ON and OFF states to adjust the capacitance between the two nodes.
    Type: Grant
    Filed: January 15, 2018
    Date of Patent: November 12, 2019
    Assignee: pSemi Corporation
    Inventor: Tero Tapio Ranta
  • Patent number: 10476512
    Abstract: The invention relates to a phase detection method (200) comprising the following steps: receiving (201) a receiving sequence (Yj) of values (Y0, Y1, . . . , YN?1) of a receiving signal (Y), said values (Y0, Y1, . . .
    Type: Grant
    Filed: October 14, 2015
    Date of Patent: November 12, 2019
    Assignee: Sonovum AG
    Inventors: Miroslaw Wrobel, Adam Kolany
  • Patent number: 10461747
    Abstract: A clock gating circuit is disclosed. The clock gating circuit includes an input circuit configured to receive an enable signal and clock enable circuitry configured to receive an input clock signal. The clock gating circuit also includes a latch that captures and stores an enabled state of the enable signal when the enable signal is asserted. An output circuit is coupled to the latch, and provides an output signal corresponding to a state of the clock signal when the latch is storing the enabled state. The clock gating circuit is arranged such that, when the latch is not storing the enabled state, no dynamic power is consumed responsive to state changes of the input clock signal.
    Type: Grant
    Filed: September 20, 2017
    Date of Patent: October 29, 2019
    Assignee: Apple Inc.
    Inventors: Vivekanandan Venugopal, Michael R Seningen, Ajay Bhatia
  • Patent number: 10418996
    Abstract: According to an embodiment, a circuit is described comprising a plurality of flip-flops, a control circuit configured to provide a control signal to each flip-flop of the plurality of flip-flops and an integrity checking circuit connected to the control circuit and to the plurality of flip-flops configured to check whether the flip-flops receive the control signal as provided by the control circuit.
    Type: Grant
    Filed: September 28, 2017
    Date of Patent: September 17, 2019
    Assignee: Infineon Technologies AG
    Inventors: Thomas Kuenemund, Molka Ben Romdhane, Berndt Gammel
  • Patent number: 10411685
    Abstract: A circuit and a method for detecting a current zero-crossing point, and a circuit and method for detecting a load voltage are disclosed.
    Type: Grant
    Filed: December 4, 2015
    Date of Patent: September 10, 2019
    Assignee: Joulwatt Technology (Hangzhou) Co., LTD
    Inventors: Pitleong Wong, Yang Lu, Yue Ji, Yuancheng Ren, Xunwei Zhou
  • Patent number: 10411675
    Abstract: In an embodiment, a delay circuit comprises a delay loop controller outputting a signal obtained by operating a start signal and a delayed feedback clock signal output from outside the delay loop controller; and a loop counter configured to determine whether a predetermined delay time has elapsed since the start signal was input according to the delayed feedback clock signal and a predetermined loop count.
    Type: Grant
    Filed: June 5, 2018
    Date of Patent: September 10, 2019
    Assignees: SK hynix Inc., Seoul National University R&DB Foundation
    Inventors: Jaewook Kim, Mino Kim, Suhwan Kim, Deog-Kyoon Jeong
  • Patent number: 10390075
    Abstract: A semiconductor device that is suitable for high-speed operation is provided. The semiconductor device includes a decoder. The decoder includes a first circuit. The first circuit is configured to operate in synchronization with a clock signal. The first circuit is configured to perform image processing. A circuit configuration of the first circuit can be changed. Clock gating is performed on the first circuit to prevent the clock signal from being input to the first circuit when the circuit configuration of the first circuit is being changed. A broadcasting system including the semiconductor device is also provided.
    Type: Grant
    Filed: October 10, 2017
    Date of Patent: August 20, 2019
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Munehiro Kozuma
  • Patent number: 10389238
    Abstract: Methods of operating a charge pump, and charge pumps configured to perform similar methods, involve monitoring a level of a supply voltage of the charge pump, and turning off an oscillator of the charge pump responsive to the level of the supply voltage dropping below a certain level, wherein turning off the oscillator comprises setting an inverter in a ring oscillator loop of the oscillator to a steady state output.
    Type: Grant
    Filed: March 21, 2018
    Date of Patent: August 20, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Ming H. Li, Dong Pan
  • Patent number: 10381051
    Abstract: A charge pump driver circuit (320) arranged to output a charge pump control signal (325). The charge pump driver circuit (320) includes a bias current source component (330) arranged to generate a bias current (335), a control stage (340) and an output stage (350). The control stage (340) is coupled to the bias current source component (330) and arranged to receive the bias current (335). The control stage (340) is further arranged to receive an input signal (215) and to generate a control current signal (345) proportional to the bias current (335) in accordance with the input signal (215). The output stage (350) is arranged to receive the control current signal (345) generated by the control stage (340) and to generate the charge pump control voltage signal (325) based on the control current signal (345) generated by the control stage (340). The bias current source component (330) is arranged to vary the bias current (335) in response to variations in temperature.
    Type: Grant
    Filed: June 7, 2017
    Date of Patent: August 13, 2019
    Assignee: NXP USA, INC.
    Inventors: Birama Goumballa, Cristian Pavao Moreira, Pierre Pascal Savary
  • Patent number: 10382014
    Abstract: An output clock frequency of an adaptive oscillator circuit changes in response to noise on an integrated circuit power supply line. The circuit features two identical delay lines which are separately connected to a regulated supply and a droopy supply. In response to noise on the droopy supply, the delay lines cause a change in the output clock frequency. The adaptive oscillator circuit slows down the output clock frequency when the droopy supply droops or falls below the regulated supply. The adaptive oscillator circuit clamps the output clock frequency at a level determined by the regulated supply when the droopy supply overshoots or swings above the regulated supply.
    Type: Grant
    Filed: December 23, 2016
    Date of Patent: August 13, 2019
    Assignees: ATI Technologies ULC, Advanced Micro Devices, Inc.
    Inventors: Joyce Cheuk Wai Wong, Dragoljub Ignjatovic, Mikhail Rodionov, Ljubisa Bajic, Stephen V. Kosonocky, Steven J. Kommrusch