Patents Examined by Patrick Chen
  • Patent number: 9973010
    Abstract: A control circuit, resonant circuit, electronic device, control method, control program, and a semiconductor element, which enable a circuit to be measured and tuned within a short time even in consideration of a time constant when a control voltage is applied to a variable capacitance capacitor. A control circuit for a variable capacitance capacitor includes: a digital-analog converter that outputs a control voltage consisting of a variable DC voltage; the variable capacitance capacitor that has a capacitance varying with an application of the control voltage; a phase detector that acquires a characteristic of a circuit containing the variable capacitance capacitor; an analog-digital converter that subjects an analog signal from the phase detector to a digital conversion; a comparing section that compares a target value with a detected value; and a control section that sets the control voltage for the digital-analog converter on the basis of the comparison result.
    Type: Grant
    Filed: June 24, 2014
    Date of Patent: May 15, 2018
    Assignee: DEXERIALS CORPORATION
    Inventor: Masayoshi Kanno
  • Patent number: 9973196
    Abstract: Apparatus for clock synchronization comprising a first phase locked loop (405) and a second phase locked loop (400). The first phase locked loop (405) is configured to receive a reference signal (Fcrystal) having a reference frequency, and operable to produce an output signal (Fout) having an output frequency that is a multiple of the reference frequency. The first phase locked loop (405) comprises a frequency divider (428) that controls the multiple in response to a control signal. The second phase locked loop (400) is configured to determine a phase error between the output signal (Fout) and an input signal (Fantenna), and to provide the control signal to the first phase locked loop (405). The second phase locked loop (400) comprises phase adjustment means (450), operable to adjust a phase difference between the input and output signal by varying the control signal for a duration.
    Type: Grant
    Filed: March 30, 2016
    Date of Patent: May 15, 2018
    Assignee: NXP B.V.
    Inventors: Jos Verlinden, Remco van de Beek, Stefan Mendel
  • Patent number: 9973032
    Abstract: Methods, systems, and apparatus, including for back-up power sources. In one aspect, a method includes providing a plurality of first battery devices, each first battery device respectively electrically coupled to a respective server rack in a plurality of server racks and having a respective capacity to provide power to the respective rack for a power anomaly for up to a first duration. Providing a second battery device electrically coupled to the plurality of server racks and having a capacity to provide power to the plurality of respective server racks for a power anomaly for up to a second duration, wherein the second duration is longer than the first duration. A power anomaly is a deviation of mains power from one or more of a nominal supply voltage and frequency.
    Type: Grant
    Filed: December 4, 2015
    Date of Patent: May 15, 2018
    Assignee: Google LLC
    Inventor: Christopher G. Malone
  • Patent number: 9966943
    Abstract: A system and method for a high-side power switch includes a gate driver configured to be coupled to a power switch, a voltage measurement circuit configured to be coupled directly to the power switch, a switch monitoring circuit configured to be coupled to the power switch, the switch monitoring circuit configured to measure an output current of the power switch, a current limitation circuit coupled to the gate driver and the switch monitoring circuit, the current limitation circuit configured to regulate gate-source voltage of the gate driver when the output current exceeds a threshold value, and a controller coupled to the current limitation circuit and the voltage measurement circuit, the controller configured to determine a mode of operation according to a startup voltage measured by the voltage measurement circuit during a startup sequence, the controller further configured to provide the threshold value to the current limitation circuit according to the mode of operation and a switch voltage measured by
    Type: Grant
    Filed: March 31, 2016
    Date of Patent: May 8, 2018
    Assignee: INFINEON TECHNOLOGIES AG
    Inventors: Christian Djelassi, Alexander Mayer, Robert Illing
  • Patent number: 9964832
    Abstract: An electronic driver circuit for use with a modulator such as a segmented Mach-Zehnder Modulator (MZM) is provided. The electronic driver circuit includes a first delay buffer implemented as a first complementary metal-oxide-semiconductor (CMOS) inverter and a second delay buffer implemented as a second CMOS inverter. The second CMOS inverter follows the first CMOS inverter and has a second gate width smaller than a first gate width of the first CMOS inverter. The first CMOS inverter is configured to produce a first delayed electrical signal from a received electrical signal and the second CMOS inverter is configured to produce a second delayed electrical signal from the first delayed electrical signal produced by the first CMOS inverter.
    Type: Grant
    Filed: May 28, 2015
    Date of Patent: May 8, 2018
    Assignee: Futurewei Technologies, Inc.
    Inventors: Morgan Chen, Yifan Gu, Hungyi Lee, Liang Gu, Yen Dang, Gong Lei, Yuming Cao, Xiao Shen, Yu Sheng Bai
  • Patent number: 9960735
    Abstract: Embodiments of a mixer of a Near field communication (NFC) receiver device and a method for operating a mixer of an NFC receiver device are disclosed. In an embodiment, a mixer of an NFC receiver device includes an input unit from which an input signal is received, a sample and hold circuit configured to sample the input signal and to store electrical charge based on the sampled input signal in order to generate a differential output signal, a control unit configured to switch the sample and hold circuit between different operational modes based on whether the input signal is a single-ended input signal or a differential input signal, and a differential output unit from which the differential output signal is output. Other embodiments are also described.
    Type: Grant
    Filed: November 2, 2016
    Date of Patent: May 1, 2018
    Assignee: NXP B.V.
    Inventors: Jingfeng Ding, Helmut Kranabenter, Gernot Hueber
  • Patent number: 9960671
    Abstract: A capacitive isolation system, capacitive isolator, and method of operating the same are disclosed. The capacitive isolation system is described to include a first semiconductor die and a second semiconductor die each having capacitive elements established thereon and positioned in a face-to-face configuration. An isolation layer is provided between the first and second semiconductor die so as to establish an isolation boundary therebetween. Capacitive coupling is used to carry information across the isolation boundary.
    Type: Grant
    Filed: December 31, 2014
    Date of Patent: May 1, 2018
    Assignee: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
    Inventors: Dominique Ho, Kwee Chong Chang, Kah Weng Lee, Brian J. Misek
  • Patent number: 9954539
    Abstract: A method, non-transitory computer readable medium, and circuit for clock phase generation are disclosed. The circuit includes an injection locked oscillator, a loop controller, and a phase interpolator. The injection locked oscillator includes an input for receiving an injected clock signal and an output for forwarding a set of fixed clock phases. The loop controller includes an input for receiving a phase separation error of the fixed clock phases and an output for forwarding a supply voltage derived from the phase separation error. The supply voltage matches the free running frequency of the injection locked oscillator to a frequency of the injected clock signal. The phase interpolator includes an input for receiving the set of fixed clock phases directly from the injection locked oscillator, an input for receiving the supply voltage from the loop controller, and an output for forwarding an arbitrary clock phase.
    Type: Grant
    Filed: July 11, 2016
    Date of Patent: April 24, 2018
    Assignee: XILINX, INC.
    Inventors: Jinyung Namkoong, Mayank Raj, Parag Upadhyaya, Vamshi Manthena, Catherine Hearne, Marc Erett
  • Patent number: 9950898
    Abstract: A semiconductor device according to an embodiment includes a plurality of circuit units each includes a first electrode, a second electrode, a switching element portion including first and second switching elements electrically connected between the first electrode and the second electrode, and a capacitor portion including a capacitor electrically connected between the first electrode and the second electrode and stacked with the switching element portion. In two of the adjacent circuit units, the switching element portion of one circuit unit and the capacitor portion of the other circuit unit are adjacent to each other, the capacitor portion of the one and the switching element portion of the other are adjacent to each other, the first electrode of the one and the first electrode of the other are adjacent to each other, and the second electrode of the one and the second electrode of the other are adjacent to each other.
    Type: Grant
    Filed: March 7, 2016
    Date of Patent: April 24, 2018
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kazuto Takao, Ryosuke Iijima, Tatsuo Shimizu, Teruyuki Ohashi
  • Patent number: 9954437
    Abstract: One charge pump includes at least one delay element, a number of inverters, and a flip flop coupled in series, with an output of one inverter coupled in a feedback loop to one of the delay elements. The charge pump monitors a first supply voltage level, and turns off an oscillator of the charge pump when the first supply voltage drops below a certain level. This is accomplished in one embodiment by monitoring a first supply voltage level supplied to a charge pump, and turning off an oscillator of the charge pump when the first supply voltage drops below a certain level.
    Type: Grant
    Filed: February 28, 2014
    Date of Patent: April 24, 2018
    Assignee: Micron Technology, Inc.
    Inventors: Ming H. Li, Dong Pan
  • Patent number: 9954538
    Abstract: A master-slave delay locked loop system comprises a master delay locked loop (“MDLL”) and at least one slave delay locked loop (“SDLL”). The MDLL generates one or more biases. Each of the at least one SDLL has a slave calibration unit and slave delay elements. The slave calibration unit calibrates the slave delay elements using a slave calibration loop and the generated one or more bias. Thus, each of the SDLL is calibrated to account for any electrical noise, pressure, voltage, and temperature variations that the respective SDLL experiences.
    Type: Grant
    Filed: June 24, 2016
    Date of Patent: April 24, 2018
    Assignee: Invecas, Inc.
    Inventors: Narasimhan Vasudevan, Venkata N. S. N. Rao, Prasad Chalasani
  • Patent number: 9952615
    Abstract: A charge pump includes a capacitor, a first transistor that is electrically connected between a first terminal of the first capacitor and ground, and a second transistor that is electrically connected between a second terminal of the first capacitor and an output node. During a first operation mode of the charge pump, a voltage that is boosted using the capacitor is output through the output node, and during a second operation mode of the charge pump, the first transistor and the second transistor are maintained in an ON state.
    Type: Grant
    Filed: March 3, 2016
    Date of Patent: April 24, 2018
    Assignee: Toshiba Memory Corporation
    Inventors: Mizuho Yoshida, Junji Musha
  • Patent number: 9953774
    Abstract: An electronic device is disclosed for controlling a high-voltage power source with multiple low-voltage switches. The electronic device includes a low-voltage DC power supply that allows for low-voltage wiring and components to be used to control the high-voltage power source using multiple low-voltage switches. The electronic device includes a single pulse generator that generates a pulse signal upon activation of any one of the multiple switches. The pulse signal activates a bistable circuit controller that is coupled the a high-voltage electronic switch to control high-voltage power to the load.
    Type: Grant
    Filed: June 29, 2015
    Date of Patent: April 24, 2018
    Inventor: Tao Liu
  • Patent number: 9954523
    Abstract: An illustrative integrated circuit configured for galvanically isolated signaling includes a receiver having: a detector module coupled to receive a differential signal from terminals of a transformer secondary, the detector module responsively presenting an impedance that varies based on a magnitude of the differential signal; a biasing module that converts the detector module impedance to a response signal; and a comparator module that compares the response signal to a reference signal to obtain a detection signal indicative of oscillation in the differential signal.
    Type: Grant
    Filed: October 18, 2016
    Date of Patent: April 24, 2018
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Richard Scott Burton, Karel Ptacek
  • Patent number: 9954375
    Abstract: The disclosure features wireless energy transfer sources that include at least two source resonators and a power source, where: each of the at least two source resonators has a nominal impedance when a device resonator is not positioned on or near any of the at least two source resonators, the nominal impedances of each of the at least two source resonators varying by 10% or less from one another; and the at least two source resonators are configured so that during operation of the wireless energy transfer source, when a device resonator is positioned on or near a first one of the at least two source resonators: (a) the impedance of the first source resonator is reduced to a value smaller than the nominal impedances of each of the other resonators by a factor of 2 or more.
    Type: Grant
    Filed: June 19, 2015
    Date of Patent: April 24, 2018
    Assignee: WiTricity Corporation
    Inventors: Alexander P. McCauley, Arunanshu M. Roy, Noam Katz, Andre B. Kurs, Morris P. Kesler
  • Patent number: 9953921
    Abstract: A semiconductor device may include a first metal line; a second metal line; a first insulating layer formed between the first metal line and the second metal line; a first driving unit coupled to the first metal line, the first driving unit being suitable for driving the first metal line in response to first data; and a second driving unit coupled to the second metal line, the second driving unit being suitable for driving the second metal line in response to second data obtained by inverting and delaying the first data.
    Type: Grant
    Filed: April 4, 2016
    Date of Patent: April 24, 2018
    Assignee: SK Hynix Inc.
    Inventor: Hyun-Bae Lee
  • Patent number: 9954517
    Abstract: Apparatuses, duty cycle adjustment circuits, adjustment circuits, and methods for duty cycle adjustment are disclosed herein. An example duty cycle adjustment circuit may be configured to receive a signal and adjust a duty cycle of the signal a first amount using a coarse adjustment. The duty cycle adjustment circuit may further be configured, after adjusting the duty cycle of the signal a first amount, to adjust the duty cycle of the signal a second amount different from the first amount using a fine adjustment to provide a duty cycle adjusted signal.
    Type: Grant
    Filed: November 6, 2012
    Date of Patent: April 24, 2018
    Assignee: Micron Technology, Inc.
    Inventor: Yantao Ma
  • Patent number: 9954536
    Abstract: One or more gray code counters, counter arrangements, and phase-locked loop (PLL) circuits are provided. A gray code counter comprises a set of cells, such as standard cells, that output a gray code signal. The gray code counter comprises a pre-ready cell that provides an early signal, generated based upon an early clock, to one or more cells to reduce delay. A counter arrangement comprises one or more counter groups configured to provide pixel count levels for pixels, such as pixels of an image sensor array. A counter group comprises a gray code counter configured to provide a gray code signal to latch counter arrangements of the counter group. A PPL circuit comprises a gray code counter configured to generate a gray code signal used by a digital filter to adjust an oscillator. The gray code signal provides n-bit early/late information to the digital filter for adjustment of the oscillator.
    Type: Grant
    Filed: April 10, 2017
    Date of Patent: April 24, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITED
    Inventor: Chih-Min Liu
  • Patent number: 9948293
    Abstract: An integrated circuit includes first and second transmitter driver circuits. The first transmitter driver circuit includes a first pull-up circuit and a first pull-down circuit that are configured as a first voltage mode driver to drive a first single-ended output signal to a first pad during a voltage mode operation. The second transmitter driver circuit includes a second pull-up circuit and a second pull-down circuit that are configured as a second voltage mode driver to drive a second single-ended output signal to a second pad during the voltage mode operation. The first and second pull-up circuits and the first and second pull-down circuits drive a differential output signal to the first and second pads during a current mode operation when the first and second transmitter driver circuits are configured as a current mode driver.
    Type: Grant
    Filed: November 8, 2016
    Date of Patent: April 17, 2018
    Assignee: Intel Corporation
    Inventor: Ker Yon Lau
  • Patent number: 9949337
    Abstract: A lighting device or lighting associated device which includes an off-line computer in addition to the controlling computer. The off-line computer is one that uses less power, but is accessible wirelessly even when the light is off-line and not receiving power. The off-line computer can be used to update the program and/or media that is stored in the lighting device.
    Type: Grant
    Filed: December 5, 2012
    Date of Patent: April 17, 2018
    Assignee: Production Resource Group, LLC
    Inventor: Chris Conti