Abstract: A device includes a first driver circuit coupled to a first bus line, where the first driver circuit includes a first delay element. The first delay element is configured to receive a first input signal and generate a first output signal. The first output signal transitions logic levels after a first delay period when the first input signal transitions from a logic high level to a logic low level. The first output signal transitions logic levels after a second delay period when the first input signal transitions from the logic low level to the logic high level. The first delay element includes a sense amplifier. The first driver circuit is configured to transmit the first output signal over the first bus line. The device also includes a second driver circuit configured to transmit a second output signal over a second bus line.

Abstract: A control unit is for a bridge circuit. The control unit may include a signal generator configured to generate first and second periodic drive signals for the bridge circuit, and determine a switch-on duration of the first and second periodic drive signals based upon a first digital data value having a first resolution. The control unit may include a controller configured to receive a second digital data value having a second resolution. The second resolution may be greater than the first resolution. The controller may be configured to generate the first digital data value so that, over periods of the first and second periodic drive signals, the first digital data value corresponds to an average of the second digital data value.

Abstract: Some embodiments include apparatus and methods having a first node to receive a supply voltage, a second node to receive a first bias voltage, a third node to receive ground potential, a first circuit branch coupled between the first and second nodes, and a second circuit branch coupled between the first and third nodes. The first bias voltage is provided to a gate of a first transistor among a plurality of transistors coupled in series. The first and second circuit branches are arranged to provide a second bias voltage to gate of a second transistor among the plurality of transistors. The value of the second bias voltage is based on a value of the first bias voltage.

Abstract: A semiconductor device includes: a first field-effect transistor configured to have a source connected to a reference potential node; a second field-effect transistor configured to have a source connected to a drain of the first field-effect transistor, and a gate connected to the source of the first field-effect transistor; a gate signal node configured to input a gate signal therein; a first resistor configured to be connected between the gate signal node and a gate of the first field-effect transistor; and a first capacitor and a switch circuit configured to be connected between a drain of the second field-effect transistor and the gate of the first field-effect transistor, in which the switch circuit is connected in series with the first capacitor.

Abstract: A reference voltage generator has a bandgap reference circuit and a negative voltage generator. The bandgap reference circuit generates a reference voltage according to at least one base-emitter voltage of at least one bipolar junction transistor. The negative voltage generator generates a negative voltage, wherein at least one base terminal of the at least one bipolar junction transistor is arranged to receive a base voltage derived from the negative voltage.

Abstract: This application relates to an active diode circuit for letting current pass in one direction and blocking current in the opposite direction. The active diode circuit comprises a transistor, a control voltage generation circuit for generating a control voltage that is supplied to a control terminal of the transistor, and a sensing circuit for detecting a quantity indicative of a current flowing through the transistor. The control voltage generation circuit generates the control voltage in dependence on the detected quantity. The application further relates to a method of controlling a transistor to function as an active diode so that current may pass in one direction and is blocked in the opposite direction.

Abstract: A method of evaluating visibility of a plurality of sub-pixel structures in a panel having a plurality of red sub-pixels, green sub-pixels, and blue sub-pixels arranged in stripes, the method including establishing a target sub-pixel structure different from the stripe sub-pixel structure of the panel by combining the plurality of pixels, and evaluating a displayed image by using the target sub-pixel structure.

Abstract: An integrated circuit is provided with an MCU, which is configured to generate a PWM control signal that is free of switching pattern information therein. A current-estimating gate driver is provided, which is responsive to the PWM signal. This gate driver is configured to drive first and second gate terminals of first and second parallel switching devices (within a hybrid switch) with gate signals that establish a second switching pattern within the hybrid switch. These gate driving operations are performed in response to measuring a first voltage associated with a terminal of the hybrid switch when being driven by gate signals that establish a first switching pattern within the hybrid switch that is different from the second switching pattern. The duty cycles of the gate signals associated with the second switching pattern are unequal and the duty cycles of the gate signals associated with the first switching pattern are unequal.

Abstract: A differential driving circuit includes a source current source, a sink current source, an H-bridge circuit, an error detector unit and a circuit network. The H-bridge circuit is connected to the source current source and the sink current source, that has a first output terminal and a second output terminal, and that generates differential output from the first output terminal and the second output terminal. The error detector unit adjusts a common mode voltage at the first output terminal and the second output terminal of the H-bridge circuit by controlling at least one of the source current source and the sink current source. The circuit network is configured by resistors and capacitors connected to the first output terminal and the second output terminal of the H-bridge circuit.

Abstract: A circuit for generating an output current and a method for generating an output current are provided. A voltage generator circuit is configured to generate at least two voltages. A digital circuit is configured to generate a pulse width modulation signal having a waveform characteristic that is controllable based on bits of configuration data received by the digital circuit. An averaging circuit is configured to receive the pulse width modulation signal and generate a bias voltage that comprises a weighted average of the at least two voltages. Weights of the at least two voltages are based on the waveform characteristic of the pulse width modulation signal. A voltage-controlled current source is configured to generate an output current based on the bias voltage.

Abstract: A phase locked loop frequency calibration circuit and a method are provided. The circuit includes a timer, a counter, a control module, a frequency divider and a voltage controlled oscillator; output of voltage controlled oscillator is connected with first input of frequency divider, output of frequency divider is connected with first input of counter, second input of frequency divider, first input of timer and second input of counter are respectively connected with first output of control module, third input of counter is connected with output of timer, output of counter is connected with first input of control module, a reference clock signal is respectively sent to second input of timer and second input of control module, the number of clocks used by frequency divider to perform frequency division on output clock signal of voltage controlled oscillator is sent to third input of control module.

Abstract: A luminaire including a housing and a light source carried by the housing. The housing may include a first and second set of light emitting elements and a lens assembly. The lens assembly may include a lens with a first refraction section having a surface smoothness within a first range, and a second refraction section having a surface smoothness within a second range. The lens assembly may include conical frustum light source receiving members located between the light source and the lens. The first and second set of light emitting elements is configured to emit light at a first and second beam angle. The light emitted by the first set and second set of light emitting elements form a combined light with a center beam and gradient wherein the center beam has a greater candle power than the gradient.

Abstract: An integrated circuit includes a low voltage differential signaling (LVDS) output circuit, a high-speed current steering logic (HCSL) output circuit, a bias control circuit, a programmable voltage reference circuit coupled to the bias control circuit, an output stage circuit coupled to the HCSL output circuit, a first plurality of switches to switchably couple the bias control circuit to the LVDS output circuit, a second plurality of switches to switchably couple the bias control circuit to the output stage circuit and to the HCSL output circuit and a logic control circuit coupled to the programmable voltage reference circuit, the first plurality of switches and the second plurality of switches. The logic control circuit is configured to activate either the LVDS output circuit or the HCSL output circuit.

Abstract: A switching circuit switches a first IGBT and a second IGBT. A control circuit is equipped with a first switching element that is configured to be able to control a gate current of the first IGBT, a second switching element that is configured to be able to control a gate current of the second IGBT, and a third switching element that is connected between an electrode of the first IGBT and an electrode of the second IGBT. The control circuit controls a turn on timing and turn off timing.

Abstract: An integrated circuit comprising, a voltage regulator circuit and a programmable low power high-speed current steering logic (LPHCSL) driver circuit coupled to a common supply voltage. The voltage regulator circuit includes a native source follower transistor having a negative threshold voltage to provide more headroom for the voltage regulator to operate. The LPHCSL driver circuit includes a plurality of selectable output driver legs and a plurality of programmable resistors. The ability to use a common supply voltage and the ability to select multiple output impedance drivers reduces the die area without increasing the complexity of the integrated circuit.

Abstract: A gate driver circuit for prevention of an arm short may include a drive controller configured to a gate drive signal, a drive signal transfer portion configured to amplify the gate drive signal and output the amplified gate drive signal, a variable resistance portion configured to change a time constant of the amplified gate drive signal using an internal resistance and output the amplified gate drive signal having the changed time constant to a gate of a semiconductor device, and a resistance controller configured to compare a first DESAT pin voltage of the drive controller with a first predetermined reference value and control the internal resistance of the variable resistance portion using the comparison result with the first predetermined reference value to perform a first driver circuit protection.

Abstract: A signal transmission circuit with a first circuit in a signal transmission side having first and second semiconductor switch elements transmitting a reference potential or power supply voltage of the first circuit to a second circuit by being alternatively driven on and off according to a multiple of signals. The second circuit in a signal reception side having a voltage conversion circuit, including an in-phase noise filter that eliminates in-phase noise superimposed on the voltage transmitted via the first and second semiconductor switch elements, generating first and second pulse signals in accordance with the transmitted voltage, a latch circuit latching each of the first and second pulse signals with the first and second pulse signals as a clock, and a signal analysis circuit analyzing the first and second pulse signals latched by the latch circuit, and generating an output signal according to the category of the multiple of signals.

Abstract: Embodiments relate to an accumulator-based phase memory. An aspect includes a phase correction calculator configured to, based on receipt of a new frequency tuning word on a frequency tuning word input, determine a phase difference between the new frequency tuning word and a current frequency tuning word, and determine a product of the phase difference and a value of a counter. Another aspect includes wherein the accumulator-based phase memory determines a phase offset value based on the product of the phase difference and the value of the counter. Another aspect includes the accumulator-based phase memory further comprising a waveform generator configured to generate a waveform based on the new frequency tuning word and the phase offset value.

Abstract: This invention pertains to a source follower circuit suitable for receiving and buffering an input voltage and providing the buffered input voltage to a sampling capacitor via a sampling switch. The source follower circuit employs a slew enhancement circuit which enables the source follower to have fast settling for both high-to-low and low-to-high transitions.

Abstract: A reverse-conducting insulated gate bipolar transistor, particularly a bi-mode insulated gate transistor, is controlled by responding to an ON command by applying high-level gate voltage for a first period, during which a current is fed into a connection point, from which it flows either through the RC-IGBT or along a different path. Based hereon, it is determined whether the RC-IGBT conducts in its forward/IGBT or reverse/diode mode, and the RC-IGBT is either driven at high or low gate voltage. Subsequent conduction mode changes may be monitored in the same way, and the gate voltage may be adjusted accordingly. A special turn-off procedure may be applied in response to an OFF command in cases where the RC-IGBT conducts in the reverse mode, wherein a high-level pulse is applied for a second period before the gate voltage goes down to turn-off level.