Abstract: A semiconductor device includes an input, a level shifter, an output, and a switch module. The input is configured to receive an input signal in a first voltage domain. The level shifter is connected to the input and is configured to shift the input signal from the first voltage domain to a second voltage domain. The switch module is configured to connect one of the input and the level shifter to the output. A method of mitigating a delay between input and output signals of the semiconductor device is also disclosed.

Abstract: A latch device includes a memory cell, a pair of write switches and an output terminal. The memory cell stores a latch data, and the pair of write switches is coupled to the memory cell through a first node and a second node. The pair of write switches holds the latch data stored in the memory cell when logic values of a first input signal and a second input signal are a predetermined logic value, and updates the latch data stored in the memory cell when the logic values of the first input signal and the second input signal are mutually exclusive logic values. The output terminal is coupled to at least one of the first node and the second node and outputs an output signal based on the latch data stored in the memory cell. An operation of the latch memory is also introduced.

Abstract: An embodiment level converter circuit is configured to receive, as a current supply, a current proportional to temperature.

Abstract: In an embodiment, an electronic circuit includes: a supply management circuit for receiving an input supply voltage and providing a first supply voltage; and a main circuit configured to: when the input supply voltage becomes higher than a first threshold, cause the electronic circuit to transition into an initialization state in which an oscillator is enabled and configuration data is copied from an NVM to configuration registers, and then to transition into a standby state in which the oscillator is disabled and content of the configuration registers is preserved by the first supply voltage, and, upon reception of a wakeup event, cause the configuration data from the configuration registers to be applied to the first circuit, and cause the electronic circuit to transition into an active state in which the first oscillator is enabled and the first circuit is configured to operate based on the configuration data.

Abstract: A signal processing circuit includes an input buffer circuit and a direct-(DC) voltage detector circuit. The input buffer circuit is coupled to a pin. The pin is configured to receive an input signal. The DC voltage detector circuit is coupled to the pin and the input buffer circuit. The DC voltage detector circuit is configured to detect the input signal to generate a mode signal and generate a bias of the input buffer circuit according to the mode signal.

Abstract: A phase-locked loop (PLL) circuit generates an analog signal in phase-lock with a reference signal at a reference frequency. The PLL circuit includes a charge pump circuit, a loop filter circuit, a feedback divider, and a voltage controlled oscillator (VCO). The charge pump circuit charges a sample capacitor of the loop filter circuit to a sample voltage based on a phase difference between the generated analog signal and the reference signal. The loop filter circuit stores the sample voltage as a proportional control voltage in a hold capacitor to reduce or avoid ripple in the control voltage that causes jitter in the analog signal. The loop filter circuit also provides the sample voltage to an integral component circuit comprising a comparator and digital accumulator producing an integral control. The VCO generates the analog signal at a frequency based on the proportional control voltage and the integral control voltage.

Abstract: A semiconductor device includes: a first latch circuit that includes a first inverting circuit, a second inverting circuit, a third inverting circuit, and a fourth inverting circuit; a first first-type well region; a second first-type well region; and a second-type well region. In a plan view, a distance between a drain of a first-type MOS transistor in the first inverting circuit and a drain of a first-type MOS transistor in the third inverting circuit is longer than a distance between the drain of the first-type MOS transistor in the first inverting circuit and a drain of a first-type MOS transistor in the fourth inverting circuit.

Abstract: A latch circuit includes a latch module, a set control module, a reset control module and a clock module, wherein the latch module is employed for latching data input by a data module, the set control module is employed for controlling the latch module to output a high-level signal, the reset control module is employed for controlling the latch module to output a low-level signal, and the clock module is employed for providing a readout clock signal to the latch module.

Abstract: A radio frequency (RF) generator includes a pulse generator circuit configured to receive input signals indicative of a pulse pattern comprising pulse segments, the input signals defining power levels and durations for the pulse segments. The pulse generator circuit generates a pulse modulation control signal for each pulse segment responsive to the input signals. The pulse modulation control signal is coupled to adjust an amplitude and to modulate an RF source signal to generate the pulse RF signal having an envelope defined by the pulse segments of the pulse pattern.

Abstract: A method system, and apparatus for adjusting skew in a circuit comprising feeding an input clock into a first push-pull source follower stage, feeding an inverse of an input clock bar into a first CMOS inverter stage, creating an output clock based on an equal contribution of the input clock of the first push-pull follower stage and the inverse of the input clock bar of the first CMOS invert stage, feeding the input clock bar into a first push-pull source follower stage, feeding an inverse of the input clock into a first CMOS inverter stage, and creating an output clock based on an equal contribution of the input clock bar of the first push-pull follower stage and the inverse of the input clock bar of the first CMOS invert stage.

Abstract: A true single-phase clock (TSPC) D flip-flop includes four stages. The four stages are serially connected between the input terminal and the output terminal of the TSPC D-type flip-flop. Each stage is selectively equipped with two connecting devices. One of the two connecting devices is a resistive element. The other of the two connecting devices is a short circuit element. When the node between two stages is in the floating state, the voltage change is slowed down by the resistive element. Consequently, the possibility of causing the function failure of the D-type flip-flop is minimized.

Abstract: The present invention discloses a signal output circuit having anti-interference mechanism. An amplifier is electrically coupled to a power supply and a ground terminal through a first and a second amplifier bond wires, and generates an amplified output signal. A transformer circuit includes a transformer performing impedance transformation on the amplified output signal to generate a transformed output signal and a voltage-stabilizing capacitor suppressing second-order harmonics of the amplifier. A power-terminal side anti-interference circuit includes a power-terminal side bond wire and a power-terminal side anti-interference capacitor. The power-terminal side bond wire is electrically coupled to the ground terminal.

Abstract: A circuit driving system, a driver chip, and a display device are provided. The circuit driving system and the driver chip are applied to a display driving of a display panel. The circuit driving system includes a timing control unit, a driving unit and, a time-sharing switch unit. The time-sharing switch unit is configured to control a switching state of the driving unit, so that the timing control unit and the driving unit in the circuit driving system are turned on step by step.

Abstract: A random number generator that includes control circuit, an oscillation circuit, an oscillation detection circuit and a latch circuit is introduced. The control circuit sweeps a configuration of a bias control signal among a plurality of configurations. The oscillation circuit generates an oscillation signal based on the configuration of the bias control signal. The oscillation detection circuit detects an onset of the oscillation signal, and outputs a lock signal. The latch circuit latches the oscillation signal according to a trigger signal to output a random number, wherein the trigger signal is asserted after the lock signal is outputted, and the configuration of bias control signal is locked after the lock signal is outputted. A method for generating a random number and an operation method of a random number generator are also introduced.

Abstract: A semiconductor device includes an output control circuit configured to generate a pre-output control signal and an output control signal according to the number of times that an output strobe pulse is inputted. The semiconductor device also includes a pipe circuit configured to generate latched data by latching input data on the basis of an input control signal, select some bits of the bits of the latched data and set the selected bits to pre-output data on the basis of the pre-output control signal, and output the pre-output data as output data on the basis of the output control signal.

Abstract: A fractional-N all digital phase locked loop (ADPLL) includes a randomly modulated delay having a triangular distribution to a frequency reference at an input of the fractional-n ADPLL to reduce spurious tones introduced by delta-sigma modulation of a frequency control word without requiring active control or calibration. In some embodiments, a delay line generates the randomly modulated delay based on a uniformly distributed random number with a flat spectrum that is shaped by a high pass filter.

Abstract: A power supply system for an electric arc furnace includes an AC input connectable to an electrical grid and an AC output for supplying at least one power electrode of the arc furnace; a resonant circuit interconnected between the AC input and the AC output. The resonant circuit includes a controllable bypass switch for connecting and disconnecting a circuit input and a circuit output of the resonant circuit and a capacitor and a main inductor connected in parallel with the bypass switch.

Abstract: A digital phase-locked loop (PLL) includes a time-to-digital converter (TDC) and a digitally controlled oscillator (DCO). The DCO generates a PLL clock signal and various sampling clock signals that are mesochronous. The TDC samples a phase difference between a reference clock signal and a frequency-divided version of the PLL clock signal based on the sampling clock signals and various enable signals. The enable signals are generated based on a calibration of the digital PLL. Each enable signal is associated with a sampling clock signal and indicates whether the associated sampling clock signal is to be utilized for sampling the phase difference. Further, the TDC generates control data indicative of the sampled phase difference. The DCO generates the PLL clock signal and the sampling clock signals based on the control data until the digital PLL is in a phase-locked state.

Abstract: A semiconductor device and a method of operating a semiconductor device are provided. The semiconductor device includes a first latching circuit and a second latching circuit coupled to the first latching circuit. The second latching circuit includes a first feedback circuit and a first transmission circuit, the first feedback circuit configured to receive a first clock signal of a first phase and a second clock signal of a second phase, and the first transmission circuit configured to receive the second clock signal and a third clock signal of a third phase. The first feedback circuit is configured to be turned off by the first clock signal and the second clock signal before the first transmission circuit is turned on by the second clock signal and the third clock signal.

Abstract: An energy harvester is provided. The energy harvester includes a current-voltage converter, a voltage-PWM converter, an analog multiplier, a sample-hold circuit, an ?-generator, and a fractional open-circuit voltage circuit.