Abstract: A first AD converting part of an AD converter converts an input voltage into a digital value of a predetermined number of bits and output the digital value to a digital output circuit and a DA converting part. The DA converting part converts the digital value into an analog value. A subtracting part outputs a difference between the analog value output from the DA converting part and the original input voltage. An amplifying part amplifies the difference output from the subtracting part. An output from the amplifying part is input to the first AD converting part via a feedback path. A subsequent output from the amplifying part is input to the second AD converting part via a branch path so as to produce a digital value of a predetermined number of bits. While the second AD converting part performs conversion, a subsequent input voltage is subjected in parallel to AD conversion by the first AD converting part.

Abstract: A position-measuring circuit is described for use with an analog position encoder of the kind comprising a code member and at least two sensors for sensing successive marks on the code member during relative movement between the code member and sensors, the sensors providing two oscillating quadrature signals. The circuit comprising means for obtaining a relatively coarse measure of position by detecting successive instants t0–t3 at which the amplitudes of the sensor signals are equal or at which the amplitude of one signal is equal to the inverse of the amplitude of the other signal. The amplitude of one of the signals or its inverse is stored at each detection instant to alternately establish relatively high and low threshold levels. A fine measure of position at an arbitrary instant T is obtained as a function of the instantaneous amplitude P of one of the signals and the difference between neighbouring high and low thresholds levels.

Abstract: An improved pipelined analog to digital converter that facilitates calibration for non-linearity errors and a method for obtaining calibration values. The analog to digital converter has a calibration mode in which the output bits for stages in the pipeline can be coupled to output pins of the device. Device pins that are used in normal operating mode to output the most significant bits of the ADC output are used in calibration mode to make available output bits of a pipeline stage being calibrated. A calibration method takes advantage of the outputs of the stages being directly observable to compute calibration values. The output bits of a pipeline stage are monitored as the analog input to the ADC is increased. A change in these bits identifies a subrange boundary. Errors are measured for values immediately above and immediately below each subrange boundary and used to compute correction factors.

Abstract: A loudspeaker control circuit includes a bit splitter, a complement module and a digital-to-analog converter. The bit splitter divides a data item representing an acoustic signal into a high order bit group and a low order bit group. The complement module determines a complement of at least one of the high order bit group and the low order bit group. The complement module may be connected in series to the digital-to-analog converter. The digital-to-analog converter converts the high order bit group and the low order bit group from a digital format to an analog format.

Abstract: An algorithmic analog-to-digital converter (ADC) includes a sample-and-hold circuit and an ADC processing unit operating in parallel and sharing a single operational amplifier. The ADC processing unit includes an MDAC with a switched capacitor topology and a sub-ADC. The ADC processing unit is clocked by an internal clock that is N times faster than the sample-and-hold clock. Each cycle is further sub-divided into two phases. During one phase the capacitors are coupled to a residue or sampled voltage provided by the MDAC, and during another phase the capacitor are coupled to a reference voltage determined by the switch control signals generated by the sub-ADC. A set of data bits is generated by the ADC processing unit during each ADC clock cycle. The N sets of data bits are added to generate the digital output stream.

Abstract: A discrete inductive-capacitive (LC) filter selects between at least two inductor banks to tune the LC filter. The filter receives an input signal that includes one or more bands of frequencies. A control signal selects a band of frequencies for processing. A first inductor bank is selected to filter a first band of frequencies, and a second inductor bank is selected to filter a second band of frequencies. A switch circuit couples the input signal to either the first inductor bank or the second inductor bank. The switch circuit selects the first inductor bank if the first band of frequencies is selected, and selects the second inductor bank if the second band of frequencies is selected. The switch circuit electrically isolates the switching of the input signal to the first and the second inductor banks, so as to enhance the Q factor of the LC filter. Circuit and techniques are disclosed to reduce parasitic capacitance in a capacitive bank that employs MOS transistors.

Abstract: An analog-to-digital converter (200) includes at least one stage (105) for converting an analog input signal into a digital output signal using a parallel quantizer (115) comparing the analog input signal with a plurality of threshold values in parallel. The analog-to-digital converter includes, for at least one selected stage (105), an estimating circuit (210,220) for estimating an analog correction signal indicative of the mean value of a quantization error of the selected stage, and a compensating circuit (440i) for at least partially compensating an offset error of the parallel quantizer (105) in the selected stage according to the analog correction signal. A method and computing system are also provided.

Abstract: A method and apparatus are provided for encoding and decoding digital information. A sequence of data words is received, wherein each data word has a running digital sum (RDS). The sequence of data words is encoded into a sequence of corresponding code words, which has a current RDS. For each data word a binary symbol is added to the data word and the data word is selectively complemented as a function of the RDS of the data word and the current RDS of the sequence of code words to form the corresponding code word.

Abstract: A compressed data table is formed from an uncompressed data table by defining a code description bit structure having a code type and a run length of data items. The code type may be configured to identify byte-length data items, word-length data items and/or one or more user-specified data items. Each run of one or more byte-length, word-length or user-specified data items in the uncompressed data table is represented in the compressed data table with a code description bit structure having an appropriately configured code type and having its run length equal to the number of byte-length, word-length or user-specified data items in the run of one or more byte-length or word-length data items, and in the case of byte-length and word-length data items each code description bit structure is followed in the compressed data table by the one or more byte-length or word-length data items.

Abstract: Methods and systems for on-chip processing of data are disclosed. Aspects of the method may include generating a plurality of data processing commands for data compression. A first string of characters may be encoded in one operating cycle utilizing the generated plurality of data processing commands for data compression. The plurality of data processing commands may comprise a branch command, a register moving command, a register setting command, a memory load command, a memory store command, and/or a register compare command. The generated plurality of data processing commands may be stored. At least a portion of the stored data processing commands may be decoded. The decoded portion of the stored data processing commands may be sequenced. The first string of characters may be acquired from a character space. The acquired first string of characters may be matched with at least one existing codeword.

Abstract: A charge balancing modulation system for digitizing the output of a variable impedance sensor utilizes synchronous excitation of the input sensor and AC coupling of the analog input signal. In one embodiment, the modulation system includes a switched excitation source for exciting the input sensor and generating an input voltage step in response, and an integrator including an input capacitor, an amplifier and an accumulation capacitor. The input capacitor AC couples the input voltage step to the integrator to form an input charge. A reference charge packet is generated in a data dependent manner and coupled to the integrator simultaneously with the input charge. The integrator integrates charge associated with the sum of the input charge and the reference charge, when applied. The modulation system generates an output data stream exhibiting a ones density proportional to the magnitude of the average input voltage step.

Abstract: A pipeline ADC has a plurality of analog-to-digital conversion units cascaded in series to form a pipeline. An error correcting method for the pipeline ADC includes during a first mode, measuring the plurality of analog-to-digital conversion units utilizing an extra analog-to-digital conversion module; calculating a plurality of correction constant sets according to digital output values of the extra analog-to-digital conversion module in the measuring step; and during a second mode, correcting output signals of the plurality of analog-to-digital conversion units according to the correction constant sets.

Abstract: A circuit with reduced power consumption comprises first and second circuits that each have periodic active and inactive phases and that switch between the periodic active and inactive phases during operation. When the first circuit is in the active phase, the second circuit is in the inactive phase, and when the second circuit is in the active phase, the first circuit is in the inactive phase. A power supply communicates with the first and second circuits and generates first and second bias signals. The power supply selectively generates the first bias signal for the first circuit during the active phase of the first circuit, the second bias signal for the second circuit during the inactive phase of the second circuit, the second bias signal for the first circuit during the inactive phase of the first circuit, and the first bias signal for the second circuit during the active phase of the second circuit. The second bias signal is less than the first bias signal.

Abstract: A time interleaved ADC system includes a delay circuit that has a dynamically adjusted speed to achieve uniformly spaced sampling intervals. The adjustment control circuit monitors the sampling pulses associated with sampling time instant for each ADC, and provides one or more control signals to the delay circuit. In one example, the adjustment control circuit employs a phase detector circuit, an integrator circuit, and a dynamic biasing circuit. In this example, the phase detector circuit evaluates the sampling pulses to generate control signals for the integrator circuit, which generates signals that are utilized by the dynamic biasing circuit to adjust the delays associated with the delay circuit. The relative positions of the sampling pulses are controlled by adjusting the delay in the delay circuit.

Abstract: An algorithmic analog-to-digital converter (ADC) includes a sample-and-hold circuit and an ADC processing unit operating in parallel and sharing a single operational amplifier. The ADC processing unit includes an MDAC with a switched capacitor topology and a sub-ADC. The ADC processing unit is clocked by an internal clock that is N times faster than the sample-and-hold clock. Each cycle is further sub-divided into two phases. During one phase the capacitors are coupled to a residue or sampled voltage provided by the MDAC, and during another phase the capacitor are coupled to a reference voltage determined by the switch control signals generated by the sub-ADC. A set of data bits is generated by the ADC processing unit during each ADC clock cycle. The N sets of data bits are added to generate the digital output stream.

Abstract: A circuit, method and microcontroller apparatus for performing an analog to digital conversion with continuously variable resolution is disclosed. The circuit includes a integrating modulator for converting an analog input signal, corresponding to an input voltage, to a digital signal at its output over an integrate time. The circuit also includes a counter with an enable input coupled to the integrating modulator output. The counter accumulates the number of cycles where the digital signal is positive during the sample period and provides a corresponding conversion result. Further, the circuit has a pulse width modulator; its output gates a clock to the counter enable input. The pulse width modulator is user programmable on-the-fly to set said integrate time and said sample period.

Abstract: An encoder suppresses effectively the high-frequency components of data to be transmitted by decreasing the changing points of serial data, thereby suppressing EMI. A changing-point counter counts changing points of n-bit data (n: a positive integer) to generate a counting result, where values of adjoining bits change at each of the changing points The changing-point counter outputting a discrimination bit which is true when the counting result exceeds a predetermined value. A code converter converts the n-bit data in such a way that bits of the n-bit data located at predetermined positions are inverted when the discrimination bit is true. A parallel-to-serial converter converts (n+1)-bit data to a (n+1)-bit serial code, the (n+1)-bit data being generated by adding the discrimination bit to an output of the code converter.

Abstract: A method for compressing a message is disclosed, comprising: identifying a block of data within the message which is found in a previous message; generating a pointer identifying the block of data in said previous message; and replacing the block of data with the pointer in the message.

Abstract: A noise suppression circuit encompasses an internal circuit, a bypass capacitor, first and second transistors. The internal circuit has high and low level terminals, and the low level terminal is connected to a low level power supply line. The internal circuit is supplied with enable and inverted enable signals. The first transistor has a first control electrode, and one main electrode is connected to the high level terminal. The first control electrode is supplied with the inverted enable signal. The bypass capacitor is connected between the other main electrode of the first transistor and the low level power supply line. The second transistor is connected between the other main electrode of the first transistor and a high level power supply line. The second transistor has a second control electrode supplied with the enable signal. The second transistor is not conductive when the internal circuit is active.

Abstract: The present invention relates to noise shaping, especially although not exclusively for digital audio signal processing; and in particular for PCM-PWM converters in a digital amplifier.