Abstract: An encoding system for encoding digital data for transmission through a communication channel is described, which includes a DCF encoder and a parity encoder operatively coupled to the DCF encoder. The DCF encoder is adapted to receive a first data sequence, and to generate a first DCF code word and a new running digital sum as functions of the first data sequence and a pre-existing running digital sum, wherein the new running digital sum is limited to a maximum absolute value. The parity encoder is operatively coupled to the DCF encoder, and adapted to receive the first DCF code word from the DCF encoder, and to generate a first interleaved parity code word as a function of the first DCF code word, and to provide the first interleaved parity code word to a channel.

Abstract: The present invention is to provide a logic circuit which assures short-circuit current reduction by using a gate which uniquely fixes the level of each node and also reduces leakage current so that the power is turned on and off quickly. Logic gates of the subject logic circuit are divided into first-type logic gate and second-type logic gates. The first-type logic gate outputs high potential under the specific status and the second-type logic gate outputs low potential under the specific status. Under the state that the high potential is supplied to the first-type logic gates and the low potential is supplied to the second-type logic gates, the power switch MOS is turned on. Further, in case of the adder, the specific status is equal to selecting a constant as an input of the adder. For general logic circuit, specific flip-flops are introduced to implement this specific status.

Abstract: A method and apparatus for interleaving bits in a first sequence is disclosed. An exemplary method comprises storing a set of offset values in at least one table, applying in order each of the set of offset values to identify an adjacent bit pair in the first sequence of the bits for a new interleaved sequence of the bits and incrementing each of the set of offset values until an upper limit is reached to further identify additional adjacent bit pairs in the first sequence of the bits for the new interleaved sequence of the bits. The table is significantly shorter, requiring less memory than that used in a conventional interleaver, particularly a GSM interleaver for half rate speech.

Abstract: A built-in-self-test apparatus for an analog-to-digital converter includes a digital-to-analog converter, a low-pass filter, a histogram analyzer and a software engine. The digital-to-analog converter is intended to generate a first signal. The low-pass filter is intended to smoothen the first signal so that an analog-to-digital converter can perform sampling on the smoothened first signal by a second signal, wherein the bit number of the second signal is greater than or equal to that of the first signal, and the frequency of the second signal is a multiple of that of the first signal. The histogram analyzer is electrically connected to the output end of the analog-to-digital converter. The software engine is electrically connected to the output end of the histogram analyzer so as to display the characteristics of the analog-to-digital converter.

Abstract: Open loop common mode driver for switched capacitor input to SAR. A method for controlling the operation of a SAR conversion cycle. The method includes the steps of first initiating the SAR conversion cycle by connecting one side of a plurality of capacitors in a capacitor array to a first capacitor reference voltage and the other side of the plurality of capacitors to the input of a comparator. This is followed by the step of sequentially switching in a plurality of compare cycles the one side of a select one or ones of the capacitors to a second capacitor reference voltage to change the voltage on the input of the comparator. Then, a compare operation is initiated after initiation of each compare cycle to compare the value on the input of the comparator with a compare reference voltage after a predetermined settling time has elapsed from the beginning of the initiation of each compare cycle.

Abstract: A modulation apparatus and method for more accurately determining a value of a control bit to be inserted into a data sequence and digital sum value (DSV) control bit generating method in which a data conversion unit supplies modulation-delimiter information including information regarding delimiters of modulation of a data sequence based on a conversion table to a modulation-delimiter detecting unit and supplies to a valid-delimiter detecting unit a DSV-segment-delimiter signal including information regarding a delimiter position of a DSV segment of the data sequence having the DSV control bit. The modulation-delimiter detecting unit detects modulation-delimiter positions based on the modulation-delimiter information supplied thereto and supplies a modulation-delimiter signal to the valid-delimiter detecting unit.

Abstract: SAR with partial capacitor sampling to reduce parasitic capacitance. An analog-to-digital convertor is disclosed with reduced parasitic capacitance on the input during a sampling operation. A charge-redistribution, binary-weighted switched-capacitor array is included having a plurality of array capacitors that each have a commonly connected plate interfaced to a first common node and a switched plate, the switched plate operable to be switched between first and second reference voltages during a redistribution phase and select ones of the capacitors additionally operable to be switched to the input during a sampling phase. Each of the array capacitors has a parasitic capacitance associated therewith. A compensation capacitor having a common plate is connected to the first common node and a switched plate, the compensation capacitor operable to be switched to the input during the sampling phase and to the first reference voltage during the redistribution phase.

Abstract: The proposed technique uses basic properties of a Huffman codebook to decode a coded data bit stream having a plurality of variable length codewords based on the Huffman codebook. This is achieved by sorting codewords in the Huffman codebook based on potential values. The potential values are computed using the basic parameters of the codewords in the Huffman codebook. A current bit sequence having a predetermined length is extracted from the coded data bit stream. A potential value of the extracted bit sequence is then computed using the basic parameters of the codewords in the Huffman codebook. The sorted Huffman codebook is then searched to find a computed potential value in the sorted Huffman codebook that is substantially close to the computed potential value of the extracted bit sequence. The extracted current bit sequence is decoded based on the outcome of the search.

Abstract: A semiconductor package contains at least one electrically isolated channel. The isolated channel is minimally susceptible to crosstalk from other channels in the package. Specifically, the level of crosstalk that may impinge on the isolated channel is below an acceptable threshold so as to permit the isolated channel to function correctly. The semiconductor package may be a FET switch assembly and the isolated channel may be used for a clock signal to prevent crosstalk contamination caused by the data signals.

Abstract: A programmable logic device (PLD) with a programmable logic core, block memory, and I/O circuitry has one or more blocks of standard-cell logic (SLBs) that are integrated into the PLD design to enable each SLB to be programmably connected to any one or more of the programmable core, the block memory, and/or the I/O circuitry. The addition of standard-cell-based functional blocks creates a PLD with increased overall logic density, a net smaller die size per function, lowered cost, and improvements to both power and performance characteristics relative to equivalent conventional PLDs, such as FPGAs.

Abstract: A coaxial transmission line having intermediary segments of equal lengths and equidistant insulator supports is provided. The transmission line segment and insulator support spacing is designed to cause any reflection artifacts to occur outside or between desired channel bands.

Abstract: A D/A converter range calibration system in an A/D converter structure including a set of comparators with associated calibrating D/A converters includes means (RCC) for determining the offset error range for the entire set of comparators and means (R-DAC) for adjusting the dynamic range of each calibrating D/A converter to this offset error range.

Abstract: A multiplexer circuit converts parallel data into serial data synchronized with an internal clock signal, and the multiplexer circuit has a logic circuit, a load circuit, and a plurality of switching elements. The logic circuit processes the internal clock signal and the parallel data. The load circuit and the plurality of switching elements are connected in series between a first power source line and a second power source line. Each of the switching elements is controlled in accordance with an output of the logic circuit.

Abstract: An RF switch includes first and second diodes characterized by an intrinsic region. Pin diodes and nip diodes are examples of such diodes with intrinsic regions. The diodes are stacked with facing first connections. A bias conductor extends from the first connections.

Abstract: A bit-and-one-half analog to digital converter comprises a switched capacitor circuit, including an opamp, that receives an analog input voltage and generates a residual analog output voltage. The switched capacitor circuit samples the analog input voltage during a sampling phase and generates the residual analog output voltage during an integration phase. A comparator generates a digital output based on the analog output voltage generated by the switched capacitor circuit. A current source communicates with the opamp and is operable to supply a first bias current to the opamp during the sampling phase and a second bias current that is greater than the first bias current to the opamp during the integration phase.

Abstract: A modulation apparatus and method for more accurately determining a value of a control bit to be inserted into a data sequence and digital sum value (DSV) control bit generating method in which a data conversion unit supplies modulation-delimiter information including information regarding delimiters of modulation of a data sequence based on a conversion table to a modulation-delimiter detecting unit and supplies to a valid-delimiter detecting unit a DSV-segment-delimiter signal including information regarding a delimiter position of a DSV segment of the data sequence having the DSV control bit. The modulation-delimiter detecting unit detects modulation-delimiter positions based on the modulation-delimiter information supplied thereto and supplies a modulation-delimiter signal to the valid-delimiter detecting unit.

Abstract: One embodiment of the invention is directed to a method comprising an act of performing digital correction of an offset in a system comprising an analog-to-digital converter (ADC) having a usable input range that is greater than a nominal input range, wherein the offset exists at an input of the ADC. Another embodiment of the invention is directed to a system comprising an ADC having a usable input range that is greater than a nominal input range, wherein an offset exists at an input of the ADC and the offset is corrected using digital correction.

Abstract: There is disclosed a recording method for performing a DSV control while recording a recording signal generated by inserting a synchronous signal for decoding reproduction data into every predetermined number of code words in a code word string satisfying a predetermined run length restriction rule and to be outputted into a recording medium, when a plurality of coding tables are used to convert an input data word of p-bits to a code word of q-bits (q>p), and the code word string obtained by directly coupling the code words is recorded and reproduced in a recording medium such as an optical disk and magnetic disk, or transmitted via a transmitting portion, wherein the p-bits are 8 bits, the q-bits are 15 bits, and the predetermined run length restriction rule stipulates that a minimum run length of the signal obtained by NRZI-converting the code word excluding the synchronous signal is 3T, and a maximum run length is any one of 11T, 12T, 13T, and 14T.

Abstract: A planar resonator and method of manufacture provides contactless power transfer using at least two electrically isolated axis aligned conductive across the transfer interface in a coupled inductor or transformer configuration. Signal or power transfer is then accomplished by coupling of magnetic flux. The coupling of electric flux is also accomplished across a same interface and driven with the same conductive spiral-wound conductors. An interface of energy transfer(IOET) has a first spiral-shaped conductor arranged on the top surface of said IOET; a second spiral-shaped conductor arranged on the bottom surface of said IOET, has a vertical axis aligned with the first spiral-shaped conductor. The IOET and the first and second spiral-shaped conductors have a predetermined self-resonant frequency.

Abstract: A modulation apparatus and method for more accurately determining a value of a control bit to be inserted into a data sequence and digital sum value (DSV) control bit generating method in which a data conversion unit supplies modulation-delimiter information including information regarding delimiters of modulation of a data sequence based on a conversion table to a modulation-delimiter detecting unit and supplies to a valid-delimiter detecting unit a DSV-segment-delimiter signal including information regarding a delimiter position of a DSV segment of the data sequence having the DSV control bit. The modulation-delimiter detecting unit detects modulation-delimiter positions based on the modulation-delimiter information supplied thereto and supplies a modulation-delimiter signal to the valid-delimiter detecting unit.