Patents Examined by Paul E Brock, II
  • Patent number: 7071039
    Abstract: A semiconductor device includes a first semiconductor region having a buried oxide layer formed therein, a second semiconductor region in which the buried oxide layer does not exist, a trench formed to such a depth as to reach at least the buried oxide layer in a boundary portion between the first and second semiconductor regions, and an isolation insulating layer buried in the trench.
    Type: Grant
    Filed: February 10, 2003
    Date of Patent: July 4, 2006
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hajime Nagano, Takashi Yamada, Tsutomu Sato, Ichiro Mizushima, Osamu Fujii
  • Patent number: 6979851
    Abstract: A structure and method is disclosed herein for a vertical transistor DRAM cell having a low leakage buried strap outdiffusion conductively connecting a storage capacitor in a lower portion of a trench to a vertical transistor thereabove. In the disclosed structure and method, the buried strap outdiffusion (BSOD) extends along a portion of the isolation collar having reduced thickness, the reduced thickness being substantially less than the thickness of the isolation collar otherwise. In a particular embodiment, a self-aligned lightly doped drain (LDD) extension is formed, extending between the BSOD and the vertical transistor above the LDD.
    Type: Grant
    Filed: October 4, 2002
    Date of Patent: December 27, 2005
    Assignee: International Business Machines Corporation
    Inventors: Dureseti Chidambarrao, Jack Allan Mandelman, Carl John Radens
  • Patent number: 6952020
    Abstract: A p channel TFT of a driving circuit has a single drain structure and its n channel TFT, a GOLD structure or an LDD structure. A pixel TFT has the LDD structure. A pixel electrode disposed in a pixel portion is connected to the pixel TFT through a hole bored in at least a protective insulation film formed of an inorganic insulating material and formed above a gate electrode of the pixel TFT, and in an interlayer insulating film disposed on the insulation film in close contact therewith. These process steps use 6 to 8 photo-masks.
    Type: Grant
    Filed: July 6, 2000
    Date of Patent: October 4, 2005
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Yasuyuki Arai, Jun Koyama
  • Patent number: 6943856
    Abstract: To provide a reflection plate and a reflection type liquid crystal display apparatus, in which a light from a light source of a fluorescent light or the sun light can be effectively used to thereby increase an amount of lights to be reflected to an observer side so that a bright display can be obtained, and a method of manufacturing the same.
    Type: Grant
    Filed: October 29, 2001
    Date of Patent: September 13, 2005
    Assignee: NEC Corporation
    Inventors: Yuichi Yamaguchi, Hidenori Ikeno, Takahiko Watanabe, Fumihiko Matsuno, Hironori Kikkawa, Michiaki Sakamoto
  • Patent number: 6933230
    Abstract: The inventor devised methods of forming interconnects that result in conductive structures with fewer voids and thus reduced electrical resistance. One embodiment of the method starts with an insulative layer having holes and trenches, fills the holes using a selective electroless deposition, and fills the trenches using a blanket deposition. Another embodiment of this method adds an anti-bonding material, such as a surfactant, to the metal before the electroless deposition, and removes at least some the surfactant after the deposition to form a gap between the deposited metal and interior sidewalls of the holes and trenches. The gap serves as a diffusion barrier. Another embodiments leaves the surfactant in place to serve as a diffusion barrier. These and other embodiments ultimately facilitate the speed, efficiency, or fabrication of integrated circuits.
    Type: Grant
    Filed: March 8, 2002
    Date of Patent: August 23, 2005
    Assignee: Intel Corporation
    Inventor: Valery Dubin
  • Patent number: 6930741
    Abstract: An active matrix LCD device includes a TFT panel, a counter panel and liquid crystal interposed therebetween. The TFT panel includes a plurality of scanning lines and a plurality of common lines formed in one layer and extending in a row direction, and a plurality of signal lines extending in a column direction. A coupling line for coupling the common lines together is disposed outside the pixel array of the TFT panel, such as in a TCP mounted on the TFT panel and mounting thereon a driver IC for driving the scanning lines.
    Type: Grant
    Filed: September 27, 2001
    Date of Patent: August 16, 2005
    Assignee: NEC LCD Technologies, Ltd.
    Inventors: Shigeru Kimura, Hiroaki Tanaka, Akira Fujita, Kiyofumi Kudou, Takahiko Watanabe, Hiroyuki Uchida, Akitoshi Maeda
  • Patent number: 6921693
    Abstract: A semiconductor device comprising: a first insulation film 60 formed above a base substrate 10; a second insulation film 61 formed on the first insulation film and having different etching characteristics from the first insulation film; and a capacitor 79 including a storage electrode 68 formed on the second insulation film, projected therefrom, the storage electrode being formed, extended downward from side surfaces of the second insulation film. The lower ends of the storage electrodes are formed partially below the etching stopper film, whereby the storage electrodes are fixed by the etching stopper film. Accordingly, the storage electrodes are prevented from peeling off in processing, such as wet etching, etc. The semiconductor device can be fabricated at high yields.
    Type: Grant
    Filed: June 26, 2002
    Date of Patent: July 26, 2005
    Assignee: Fujitsu Limited
    Inventors: Osamu Tsuboi, Tomohiko Tsutsumi, Kazutaka Yoshizawa
  • Patent number: 6916712
    Abstract: An improved trench MOS-gated device comprises a monocrystalline semiconductor substrate on which is disposed a doped upper layer. The upper layer includes at an upper surface a plurality of heavily doped body regions having a first polarity and overlying a drain region. The upper layer further includes at its upper surface a plurality of heavily doped source regions having a second polarity opposite that of the body regions A gate trench extends from the upper surface of the upper layer to the drain region and separates one source region from another. The trench has a floor and sidewalls comprising a layer of dielectric material and contains a conductive gate material filled to a selected level and an isolation layer of dielectric material that overlies the gate material and substantially fills the trench. The upper surface of the overlying layer of dielectric material in the trench is thus substantially coplanar with the upper surface of the upper layer.
    Type: Grant
    Filed: November 9, 2001
    Date of Patent: July 12, 2005
    Assignee: Fairchild Semiconductor Corporation
    Inventors: Christopher B. Kocon, Jun Zeng
  • Patent number: 6911353
    Abstract: A lead frame has an array of mounting portions connected by joint bars, and each of the mounting portions has an island serving as an external connection terminal and a plurality of lead terminals extending from the island and serving as external connection terminals for a semiconductor chip to be mounted on an adjacent island along the array. An electrically conductive paste is applied to the island, and a semiconductor chip is mounted on the island. Then, the semiconductor chip is electrically connected to the lead terminals by wires. A resin layer is deposited over the semiconductor chip, a principal surface of the island, and principle surfaces the lead terminals, while leaving opposite surfaces of the island and the lead terminals exposed. A region surrounding the island and the lead terminals electrically connected to the island is cut off into a package.
    Type: Grant
    Filed: May 2, 2002
    Date of Patent: June 28, 2005
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Takayuki Tani, Takashi Sekibata, Haruo Hyodo
  • Patent number: 6911357
    Abstract: The present invention provides a method and apparatus which facilitates wafer level burn-in testing of semiconductor dies. Sacrificial busses on the wafer supply voltage to respective on die Vcc and Vss sacrificial voltage pads during burn-in testing. The Vcc sacrificial pad on each die is connected to a secondary Vcc pad through an on-die sacrificial metal bus. An on-die fuse is interposed between the secondary Vcc pad and a normal Vcc die bonding pad. The fuse will blow when a die draws excessive current isolating a defective die from other dies on the wafer which are connected to the sacrificial busses. The Vss sacrificial pad is connected to a normal Vss die bonding pad through a sacrificial metal bus. After burn-in testing, the structures are removed. During this removal, the on-die sacrificial metal busses protect the secondary Vcc pad and Vss bonding pad. The secondary Vcc pad, Vcc bonding pad and Vss bonding pad can then be exposed for additional die testing.
    Type: Grant
    Filed: June 21, 2002
    Date of Patent: June 28, 2005
    Assignee: Micron Technology, Inc.
    Inventor: Kevin M. Devereaux
  • Patent number: 6908828
    Abstract: Processes that may be used in producing electronic, optoelectronic, or optical components may be provided. The processes may involve preparing a reusable donor wafer for donating a thin layer of semiconductor material by assembling a donor layer of a semiconductor material having a thickness of plural thin layers onto a support layer of. The semiconductor material for the support layer may be selected to be less precious or to have a lower quality than the donor layer. The support layer may have sufficient mechanical characteristics for supporting the donor layer during desired semiconductor processing treatments.
    Type: Grant
    Filed: July 12, 2004
    Date of Patent: June 21, 2005
    Assignee: S.O.I. TEC Silicon on Insulator Technologies S.A.
    Inventors: Fabrice Letertre, Thibaut Maurice
  • Patent number: 6906342
    Abstract: An optical detecting sensor includes a sensor thin film transistor generating an optical current in response to incident light reflected from an object; a storage capacitor storing charges of the optical current generated in the sensor thin film transistor; and a switch thin film transistor controlling release of the stored charges of the storage capacitor to an outer circuit for display of image of the object, having dual-layered source and drain electrodes of transparent conducting material and metal material, an active layer and a gate electrode. The switch thin film transistor further includes an ohmic contact layer on the active layer through which the dual-layered drain and source electrodes contact the active layer.
    Type: Grant
    Filed: December 20, 1999
    Date of Patent: June 14, 2005
    Assignee: LG. Philips LCD Co., Ltd.
    Inventors: Youn Gyoung Chang, Jeong Hyun Kim, Jae Kyun Lee
  • Patent number: 6903431
    Abstract: This invention relates to an apparatus and methods for reducing the impedance mismatch problem encountered by differential signaling in conductive core substrates, while maintaining adherence to the common mode noise assumption. Specifically, the conductive paths that traverse through the conductive core are separated by a nonconductive material which minimize impedance and interruption of the signal coupling.
    Type: Grant
    Filed: May 28, 2003
    Date of Patent: June 7, 2005
    Assignee: Intel Corporation
    Inventor: Jianggi He
  • Patent number: 6900110
    Abstract: A wafer level fabricated chip scale integrated circuit package having an air gap formed between the integrated circuit die of the package and compliant leads located over and conductively attached to the die is described. Contact bumps offset on the compliant leads provide for connection of the integrated circuit package to other substrates. In some embodiments, the compliant leads include a conductive layer overlaid with an outer resilient layer, and may further include an inner resilient layer beneath the conductive layer. The outer resilient layer has a via formed through it exposing the underlying conductive layer. The via is offset along the compliant lead a horizontal distance from the bond pad to which the compliant lead is conductively coupled. The chip scale package provides a highly compliant connection between the die and any substrate that the die is attached to.
    Type: Grant
    Filed: December 13, 2002
    Date of Patent: May 31, 2005
    Assignee: National Semiconductor Corporation
    Inventors: Hem P. Takiar, Nikhil Vishwanath Kelkar
  • Patent number: 6897083
    Abstract: A micro-electromechanical actuator and related methods of use that use a pair of electrodes separated by a linkage. The linkage is biased to a neutral position wherein the electrodes are spaced apart from each other, but also allows at least one electrode to move toward the other electrode when an appropriate force, such as voltage from the power source, is applied to the electrodes. The linkage is sized and shaped to allow the electrodes to move together when a defined threshold voltage is applied by the power source, thereby allowing the micro-elecromechanical actuator to function as a manufacturing quality testing device or a micromechanical actuator in other applications. The actuator may be fabricated simultaneously with other micromechanical and micro-electromechanical components on the same substrate using conventional semi-conductor and micro-machining manufacturing equipment.
    Type: Grant
    Filed: June 12, 2003
    Date of Patent: May 24, 2005
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventor: Donald J. Milligan
  • Patent number: 6897137
    Abstract: A process for fabricating ohmic contacts in a field-effect transistor includes the steps of: thinning a semiconductor layer forming recessed portions in the semiconductor layer; depositing ohmic contact over the recessed portions; and heating the deposited ohmic contacts. The field-effect transistor comprises a layered semiconductor structure which includes a first group III nitride compound semiconductor layer doped with a charge carrier, and a second group III nitride compound semiconductor layer positioned below the first layer, to generate an electron gas in the structure. After the heating step the ohmic contacts communicate with the electron gas. As a result, an excellent ohmic contact to the channel of the transistor is obtained.
    Type: Grant
    Filed: June 19, 2003
    Date of Patent: May 24, 2005
    Assignee: HRL Laboratories, LLC
    Inventors: Nguyen Xuan Nguyen, Paul Hashimoto, Chanh N. Nguyen
  • Patent number: 6881603
    Abstract: A phase change memory with a very limited area of contact between the lower electrode and the phase change material may be formed by defining a closed geometric structure for the lower electrode. The lower electrode may then be covered. The covering may then be opened in a very narrow strip extending across the closed geometric shape using phase shift masking. A phase change material may be formed in the opening. Because the opening effectively bisects the closed geometric structure of the lower electrode, two very small contact areas may be created for contacting the lower electrode to the phase change material.
    Type: Grant
    Filed: November 19, 2002
    Date of Patent: April 19, 2005
    Assignee: Intel Corporation
    Inventor: Stefan K. Lai
  • Patent number: 6876019
    Abstract: To transfer signal charges at high speed with small noise, there is provided a charge transfer apparatus including a semiconductor substrate of one conductivity type, a charge transfer region of a conductivity type opposite to that of the semiconductor substrate that is formed in the semiconductor substrate and joined to the semiconductor substrate to form a diode, a signal charge input portion which inputs a signal charge to the charge transfer region, a signal charge output portion which accumulates the signal charge transferred from the charge transfer region, and a plurality of independent potential supply terminals which supply a potential gradient to the semiconductor substrate, wherein the signal charge in the charge transfer region is transferred by the potential gradient formed by the plurality of potential supply terminals.
    Type: Grant
    Filed: November 29, 2002
    Date of Patent: April 5, 2005
    Assignee: Canon Kabushiki Kaisha
    Inventor: Mahito Shinohara
  • Patent number: 6875653
    Abstract: A memory device that includes a semiconductor substrate, and an array of memory cells, each cell being electrically isolated from adjacent cells and including an island formed from the substrate, the island having a top portion and at least one sidewall portion, and being spaced apart from other islands by a bottom surface on the substrate, a capacitor formed contiguous with the sidewall portion, and a transistor formed on the top portion of the island, the transistor including a gate oxide layer formed on a surface of the top portion, a gate formed on the gate oxide layer, and a first and a second diffused regions formed in the top portion, the first diffused region being spaced apart from the second diffused region.
    Type: Grant
    Filed: August 2, 2002
    Date of Patent: April 5, 2005
    Assignee: ProMOS Technologies Inc.
    Inventor: Ting-Shing Wang
  • Patent number: 6870197
    Abstract: A dual panel type organic electroluminescent device includes first and second substrates bonded together by a seal pattern, the first and second substrates including a plurality of sub-pixel regions, a plurality of array elements including a plurality of thin film transistors on the first substrate, a plurality of organic electroluminescent diodes on the second substrate, each of the organic electroluminescent diodes having a first electrode on a rear surface of the second substrate, an organic electroluminescent layer on a rear surface of the first electrode, a second electrode on a rear surface of the organic electroluminescent layer that corresponds to respective ones of the sub-pixel regions, a plurality of connecting electrodes connected to the thin film transistors over the first substrate, a plurality of electrical connecting patterns formed on each of the connecting electrodes, each of the electrical connecting patterns electrically interconnecting each of the thin film transistors to one of the organ
    Type: Grant
    Filed: June 30, 2003
    Date of Patent: March 22, 2005
    Assignee: LG. Philips LCD Co., Ltd.
    Inventors: Jae-Yong Park, Choong-Keun Yoo, Ock-Hee Kim, Nam-Yang Lee, Kwan-Soo Kim