Abstract: This invention addresses the need to map information from databases and reports to a new dimension of structured, intelligent interpretations or diagnostics of that information, and then querying in a coordinated manner both the original information and the resultant diagnostics databases. The invention combines elements currently available in decision support tools, programming languages and expert system building tools. First, querying mechanisms for the information in reports and databases is provided. Second, both a test processing engine and an Expert System run a set of if-then-else tests and expert rules on said information, and the resulting coded diagnostics are stored in a diagnostics database.

Abstract: A linear calculating equipment comprises a memory for storing a coefficient matrix, a known vector and an unknown vector of a given system of linear equations, a pivoting device for choosing pivots of the matrix, a plurality of preprocessors for executing K steps of preprocessing for multi-pivot simultaneous elimination, an updating device for updating the elements of the matrix and the components of the vectors, a register set for storing values of the variables, a back-substitution device for obtaining a solution and a main controller for controlling the linear calculating equipment as a whole.

Abstract: An improved small electronic apparatus such as an electronic organizer is disclosed. In the apparatus, data to be kept stored is prevented from being erroneously deleted. This apparatus comprises: a memory, a plurality of input keys; a temporary deletion element for, when a first predetermined key operation is performed, setting desired data which is stored in the memory into a temporary deletion state; a deletion element for, when a second predetermined key operation is performed, deleting the data which has been set into the temporary deletion state from the memory; and a release element for, when a third predetermined key operation is performed, releasing the temporary deletion state of the data which has been set into the temporary deletion state.

Abstract: An array processing system has a plurality of processing elements, each of which includes a processor and an associated memory module, and a router network over which each processing element can transfer messages to other random processing elements. The system further includes a shift register which can shift data either toward a shift-in terminal, or toward a shift-out terminal, either one bit at a time or four bits at a time, thus improving processing system speed for floating point arithmetic operations.

Abstract: A super scalar computer architecture and method of operation for executing instructions out-of-order while managing for data dependencies, data anti-dependencies, and integrity of sequentiality for precise interrupts, restarts and branch deletions. Multiple registers and tables are used to rename and recycle source and destination addresses referenced to a general purpose register. Access to destination data in the general purpose register is locked until the instruction associated with the data is fully executed. Renaming of both the source and destination registers avoids anti-dependency problems while integrity of sequentiality is maintained by ordered retirement of instruction results consistent with the order of the input instructions. The system and method operate with multiple input instructions and multiple execution units.

Abstract: A sequencer controller for nuclear magnetic resonance imaging includes a level-sensitive external gating arrangement. When a sequencer microcode WAIT instruction is executed, the gating arrangement operates differently depending on the level of the signal existing at the external gating input. If the external gating signal level is at one level, the gating arrangement causes the sequencer to wait until the external gating input changes level----thus permitting an external gating event (e.g., closure of a breath switch or the like) to interact with and control the timing of the NMR sequence. If the external gating signal is at a different level when the WAIT instruction is first executed, however, the sequencer does not "wait" at all but instead ignores the WAIT instruction and goes to the next sequencer state.

Abstract: Vector shifting elements of a vector register by varying amounts in a single process is achieved in a vector supercomputer processor. A first vector register contains a set of operands, and a second vector register contains a set of shift counts, one shift count for each operand. Operands and shift counts are successively transferred to a vector shift functional unit, which shifts the operand by an amount equal to the value of the shift count. The shifted operands are stored in a third vector register. The vector shift functional unit also achieves word shifting of a predetermined number of vector register elements to different word locations of another vector register.

Abstract: An adapter which attaches Data Terminal Equipment (DTE) to a LAN includes a latch whose state is changed by conditions, such as a free token or a frame, on the LAN. The output of the latch is used to calculate the bandwidth utilization of the LAN.

Abstract: A real time data processing system consisting of a plurality of processing nodes and a write only reflective data link for transferring information containing writes only between the plurality or processing nodes. All the nodes include a bus, a processor coupled to the bus, a memory having at least two ports with one port connected to the bus and the other port connected to the data link and a sensor for sensing a write to the memory. At least one node has a VMEbus as the bus and serves as an I/O connected to one port of the memory. Further a local bus included for inputting and outputting from the memory. The local bus is connected to a third port of the memory.

Abstract: The Lambda network is a single stage, packet-switched interprocessor communication network for a distributed memory, parallel processor computer. Its design arises from the desired network characteristics of minimizing mean and maximum packet transfer time, local routing, expandability, deadlock avoidance, and fault tolerance. The network is based on fixed degree nodes and has mean and maximum packet transfer distances where n is the number of processors. The routing method is detailed, as are methods for expandability, deadlock avoidance, and fault tolerance.

Abstract: A system and method for parallel execution of logic programs on a computer network comprising two or more local-memory processors includes a logic program interpreter resident on all processors in the system. The interpreter commences execution of a logic program on one processor and, based on the results of its initial execution, generates lists of parallel-executable tasks and distributes them to other processors in the network to which it is coupled. Each processor which receives parallel tasks likewise commences execution, identification of parallel sub-tasks, and further distribution. When there are no parallel tasks at a processor or other processors available for further distributions, the task is executed sequentially and all execution results are returned to the processor which distributed the tasks executed.

Abstract: A multi-processing computer system has multiple computing units. Each of the computing units includes a processor linked to a private memory via a private data bus, and each computing unit is linked to every other computing unit by a respective separate independent shared memory area. The shared memory areas are controlled by a communications controller which can provide a fully asynchronous two-way communication route through the memory area. The multitasking capabilities of the computer are further controlled by a set of unit controllers in combination with respective software task schedulers.

Abstract: Event driven logic simulator for partial simulation is provided. An event storage has an event attribute storage section for indicating whether an event is preset before the execution of simulation by the operator. The node information storage has an event propagation flag storage indicating whether or not an event which has occurred during the execution of simulation will be transmitted. When the event propagation flag is off, the content of the event attribute section is determined. When a section indicates the event is preset by user, the event is propagated. Otherwise, the event is skipped. The operator can inject a signal pattern into a node by setting the event propagation flag of the node off and by registering events for that node representing the input signal pattern.

Abstract: A computer-based system, such as a value printing system, has a host data processor having at least one disk drive that includes a first read/write head for reading data from and for writing data to a removable data recording disk. The system further includes a printer, coupled to the host data processor and responsive thereto, for printing indicia indicative of a monetary value. The system further includes a removable data recording disk having an integral data processor including a memory for storing data expressive of a monetary value associated with printed indicia. The integral data processor further includes a second read/write head coupled to the recording medium for communicating with the host data processor through the first read/write head.

Abstract: A data control device which acquires the right to use a bus and performs data control includes a request circuit which selectively generates a plurality of request signals for acquiring the right to use corresponding buses. The plurality of request signals are based on attributes of data to be exchanged with an external device. The exchanged data includes data and commands.

Abstract: In a data processing system, an input output bus unit (IOBU) is connected to one end of an input output interface controller (IOIC) via an asynchronous bus. The other end of the IOIC is connected to a storage controller (SC) and an input output interface unit (IOIU) via a synchronous bus. The SC and IOIU are connected to a memory unit and an instruction processing unit. The asynchronous bus, which is comprised of three sub-buses and a control bus, conducts signals between the IOIC and an IOBU in an asynchronous "handshaking" manner. The synchronous bus, which is comprised of two sub-buses and a control bus, conducts signals between the IOIC and the SC/IOIU in an synchronous manner. The IOIC, interconnected between the synchronous bus and asynchronous bus, functions as a buffer between the faster synchronous bus and the slower asynchronous bus.

Abstract: A system and method for booting a client workstation from a remote data processing system over a network includes initializing the client workstation sufficiently to establish network communications with a remote disk on the remote data processing system, establishing a network communications link between the local and remote systems, issuing a request from the client workstation to the remote data processing system over the network communications link for a task image code module for providing a network interface between the client workstation and the remote disk on the remote data processing system, downloading the task image code module from the remote to the client workstation in response to the request for the task image code module, invoking the task image code module by the client workstation to establish a network interface between the client workstation and the remote disk, copying an image of the remote disk over the network to the client workstation to create a local disk image stored in the client

Abstract: A data processing apparatus having one or more processors each comprising an optical vector matrix multiplier and its peripheral circuits mounted on a single semiconductor substrate, the multiple processors constituting a network. The components of the optical vector matrix multiplier may be divided on two semiconductor substrates so that light-borne data is exchanged therebetween. These arrangements provide a compact multifunction data processing apparatus adapted to deal flexibly with diverse computing problems.

Abstract: An application event collector which is embodied in computer software that collects event-based data. The collector follows a process which includes the steps of: (a) storing definitions of event-marking instructions that have been embedded in the software application, each instruction being capable, when enabled, of collecting event-based data, and the definitions identifying the software application in which the instructions have been embedded and the type of data collected by the instructions; (b) selecting, prior to or during execution of the application, a subset of the event-marking instructions and enabling those instructions; and (c) detecting the enabled event-marking instructions, during execution of the software application, and collecting the data specified by the enabled instructions. The application is divided into layers, each of which may have event-marking instructions embedded in it.

Abstract: The subject invention is directed to a database system for organizing large amounts of data to be accessed by a digital computer. More particularly, a free form type database, in the form of a summarized, multikey tree, is built from files stored on the computer. After a building operation, the user obtains specified information by using the summarized database. Information in the files is divided into three categories; that is, a dimension field which comprises data to be organized, a summary field which comprises a numeric quantity on which calculations can be performed, and a non-summary field which comprises other information associated with an input record. The internal nodes of the tree summarize and organize sets of input records. Methods are provided for reducing the amount of storage space used by cutting off the tree when the size of sets go below a given threshold, and sharing parts of the tree so that each record does not appear n! times in the database.