Abstract: False transitions resulting from capacitive coupling between parallel interconnects driven by dynamic circuits are reduced by classifying interconnects based on the timing of expected data transitions in the signals they carry. Interconnects carrying signals expected to transition during a first portion of a processor cycle are treated as one category, while interconnects carrying signals expected to transition during a second, different portion of the processors cycle are treated as a second category. Interconnects of different categories are interdigitated, a resets of dynamic driving circuits are tuned so that, at any given time, alternate interconnects are “quiet” or stable. Therefore interconnects being driven with data transitions are directly adjacent to quiet lines, and foot devices are implemented as necessary to prevent coupling expected during the reset phase.

Abstract: In a method of processing figure arrays in a figure processing apparatus, first and second figure arrays are sequentially inputted. A fractionalizing process is selectively performed to divide each of figure elements of the second figure array into a plurality of types of fractions based on presence/non-presence of an overlapping portion between the first and second figure arrays and an array data of the second figure array. The array data indicates an array pitch in each of horizontal and vertical directions and a number of figures in the direction. A figure array of fractions is produced for each type and the produced figure arrays is registered in chain groups which includes a chain group of the first figure array, such that the registered figure arrays have the same array data. Then, a figure operating process is performed to the chain group.

Abstract: A method of modifying a layout of a plurality of objects in accordance with a plurality of predetermined criteria is presented. An objective function is defined for measuring a location perturbation and a separation perturbation of the objects in the layout. A linear system is defined using linear constraints in terms of design rules and the objective function to describe separations between layout objects. The linear system is solved to simultaneously remove violations of the design rules, and shapes and positions of objects in the layout are modified in accordance with the solution of the linear system such that a total perturbation of the objects in the layout is reduced. A system for implementing the present invention is also presented.

Abstract: A method and device for scoping global nets from a schematic in a flat netlist. The device is a complementary subsystem to a flat netlister software package. The device allows instances in a schematic to systematically reassign global nets to local nets so that the use of such nets does not affect usage of the global nets elsewhere in the circuit. The device tracks all global nets and maps the corresponding scoped nets to their net identifiers. Then, as the netlister creates the flat netlist, the device replaces the global net's net identifier with the correct net identifier of the corresponding scoped net.

Abstract: A method for calculating density maps in hierarchical designs includes the steps of deoverlapping objects in the design, providing an area of interest in the design, generating a grid in the area of interest to partition the area of interest into grid elements, determining whether the local properties of each object within the grid elements have been previously calculated, if previously calculated, adding the previously calculated value for the local properties to a corresponding grid element, otherwise, calculating the local properties of the object and summing the local properties of the objects for each associated grid element such that the local properties are calculated only once for a given object throughout the design. A system is also includes for implementing the method.

Abstract: The design for testability method of this invention forms scan paths in a circuit preliminarily-designed with required elements. According to this design method, a plurality of appropriated paths that can be appropriated as scan paths are extracted from the multiplicity of path of the circuit, occupied areas are individually calculated for each of the plurality of appropriated paths both for cases in which scan paths are formed using multiplexers and for cases in which registers are replaced by scan elements, and in each case the scan path having the smaller occupied area is selected and formed. The two types of methods for forming scan paths are selected for each portion of the circuit, thereby allowing scan paths to be formed with the smallest occupied area in the circuit.

Abstract: A computerized tool or method that calculates the capacitance and resistance of each global wire on the chip, one wire at a time. The invention steps along a track containing a wire segment, grid point by grid point, calculating the resistance and capacitance at that point. At each grid point it searches the neighboring tracks within the surrounding cube for adjacent elements that could cause capacitive effects or affect the resistance of the wire. The method delivers capacitance and resistance values for each process condition for a grid unit length of wire, given the wire type and 3 dimensional environment of the wire segment. The capacitance and resistance at a grid point along the wire are generally determined by one table lookup for wire types based on the surrounding environment. These values are added along wire segments to deliver accurate 3 dimensional capacitances and resistances.

Abstract: A checking routine verifies a phase shifted mask (PSM) design based on fundamental principles of PSM and utilizing only basic shape manipulation functions and Boolean operations found in most computer aided design (CAD) systems. The design verification system checks complete chip designs for the two possible design errors that can cause defective masks by eliminating the phase transition; namely, placing a 180° phase region on both sides of a critical feature or completely omitting the phase region adjacent to certain critical features.

Abstract: An electronic data mining process for mining from an electronic data base using an electronic digital computer a listing of commercially useful information of the type known in the art as an association rule containing at least one uninstantiated condition. For example, the commercially useful information may be information useful for sales promotion, such as promotion of telephone usage. The computer retrieves from the database a plurality of stored parameters from which measures of the uninstatiated condition can be determined. The computer uses a dynamic programming algorithm and iterates over intervals or sub-ranges of the parameters to obtain what is called an at least partially optimized association rule, as optimized intervals or sub-ranges of at least some of the retrieved parameters, for example, time intervals of high usage of certain types of telephone connections. These optimized intervals are provided as the listed commercially useful information.

Abstract: An apparatus includes a master latch of a master/slave flip-flop, wherein the master latch includes a first data output. The apparatus also includes a logic coupled to receive the first data output, wherein the logic includes a second data output without using a slave latch of a master/slave flip-flop, and a non-slave latch coupled to receive the second data output.

Abstract: System and method for verifying data in forms. Each form has a corresponding one or more rule sets each with rules that designate a structure, format, or data type for fields in the form. The rule sets are verified in parallel. Rules within a rule set may also be verified in parallel when the processor determines it is beneficial such as for time consuming rule validation.

Abstract: A modification to the available simulated annealing algorithm is provided to better utilize direct connects and other architecture-specific features of a Field Programmable Gate Array. A preferred embodiment comprises adding a template-based move to the SA move-set that recognizes a specific pattern or template in the user's design after mapping, and arranges the components into the optimal configuration for the specific template discovered. The present invention increases the intelligence of the SA move-set by selectively supplementing the random moves in the move-set with moves that produce locally good solutions.

Abstract: The invention provides a method of design for testability in which design of an integrated circuit is modified, at a register transfer level (RTL) with high abstraction than the gate level, so as to be simply testable and in which the area of a test circuit and the number of test patterns can be decreased as compared with those in the conventional method. An integrated circuit which has been designed in an RTL design step is partitioned into blocks each satisfying a previously defined simply testable condition in a partitioning step, so that the integrated circuit can be simply tested after manufacture. The simply testable condition can be that a circuit has an acyclic structure including no feedback loop, that a circuit has an n-fold line-up structure (wherein n is a positive integer), or the like.

Abstract: A methodology is implemented for accurately and precisely computing the output signal times for clock circuit in a data processing system (600) using transistor-level static timing analysis tools which compute delays of blocks or subcircuits that correspond to channel-connected components of transistors. During execution of the Static timing analysis, the predictability of clock signals is recognized and denoted in a timing model (616-622). Furthermore, an actual logical function of the clock circuit is determined during execution of the static timing analysis to provide more precise knowledge of the rise and fall times of the signals provided to the clock circuit.

Abstract: A method of partitioning logic into a programmable logic device includes the steps of synthesizing a logic design into a network of hierarchical components. Each hierarchical component is then mapped to a minimum number of logic array blocks in a programmable logic device. The mapping operation may be performed by independently synthesizing the hierarchical components into a network of virtual logic elements, assigning the virtual logic elements to virtual logic array blocks, and mapping the virtual logic array blocks to the logic array blocks in the programmable logic device.

Abstract: A system and method for efficiently designing integrated circuits provides a verification manager for verifying an integrated circuit design, a synthesis manager for synthesizing the integrated circuit design, a backend manager for implementing the integrated circuit design, and a processor for simultaneously controlling the verification manager, the synthesis manager, and the backend manager to create the integrated circuit design. The system and method generates a series of regression checkpoints controlled by the verification manager, and a series of timing checkpoints controlled by the synthesis manager to facilitate and expedite the integrated circuit design procedure.

Abstract: A modular distributed I/O system includes a computer coupled to module banks through a network bus. A module bank includes a communication module, terminal bases, and I/O modules. The adjoined terminal bases form a local bus mastered by the communication module. The I/O modules connect to the local bus through terminal bases. I/O modules are pluriform and programmable. The communication module maintains a memory image of the configuration state of each I/O module resident in the module bank. A memory image persists when an I/O module is removed from its terminal base. The memory image is used to configure a new I/O module which is inserted into the same terminal base. The communication module monitors for communication failure on the network bus, and is configured to capture the state of the module bank and automatically restore this captured state after a power-loss event. The terminal bases realize a local bus which includes a parallel bus, a serial bus, and an address assignment bus.

Abstract: Routing layers are assigned to connection segments in integrated circuit design. A routing description that includes connection segments and a vertex where at least two of the connection segments connect to each other is obtained. A penalty is determined for the vertex based on a potential layer assignment combination for the connection segments that connect at the vertex, and routing layers are assigned to the connection segments based on the determined penalty.

Abstract: Methods and apparatus for performing non-linear analysis using preconditioners to reduce the computation and storage requirements associated with processing a system of equations. A circuit, system or other device to be analyzed includes n unknown waveforms, each characterized by N coefficients in the system of equations. A Jacobian matrix representative of the system of equations is generated. The Jacobian matrix may be in the form of an n×n sparse matrix of dense N×N blocks, such that each block is of size N2. In an illustrative embodiment, a low displacement rank preconditioner is applied to the Jacobian matrix in order to provide a preconditioned linear system. The preconditioner may be in the form of an n×n sparse matrix which includes compressed blocks which can be represented by substantially less than N2 elements.

Abstract: The invention provides a cell placement method and apparatus wherein an area for cell's placement is assured to place cells as many as possible to be placed efficiently on a single chip and a storage medium on which a cell placement program which allows such placement is stored. In the cell placement method and apparatus, in order to design an integrated circuit having a plurality of routing layers, when to place cells in a situation wherein a wire is already routed prior to the placement of the cells is present, placement of each of the cells at a position at which the cell overlaps with the already routed wire is permitted unless a wiring pattern in the cell and the already routed wire overlap with each other in a same routing layer.