Patents Examined by Peguy JeanPierre
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Patent number: 7965211Abstract: A power amplifier architecture includes a plurality of non-linear optically driven power amplifier modules. The plurality of non-linear optically driven power amplifier modules are selectively connectable utilizing a programmable algorithm for combining at least two modules of the plurality of non-linear optically driven power amplifier modules in a time sequence yielding a piecewise approximation of a continuous waveform. The power amplifier architecture further includes at least one RF drive selectively connected to at least one of the plurality of non-linear optically driven power amplifier modules via an optical signal link generating a separate drive signal for each of the plurality of non-linear optically driven power amplifier modules.Type: GrantFiled: November 9, 2009Date of Patent: June 21, 2011Assignee: Rockwell Collins, Inc.Inventors: Don L. Landt, Allen W. Jones, Scott Zogg
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Patent number: 7961124Abstract: A device and process to compensate for asymmetrical qualities of an analog input signal, if present, and generate a timing signal. The timing signal is then used for analog to digital conversion.Type: GrantFiled: April 3, 2009Date of Patent: June 14, 2011Assignee: Marvell International Ltd.Inventors: Jingfeng Liu, Mats Oberg, Zachary Keirn, Bin Ni
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Patent number: 7961119Abstract: A network optimization device may receive a stream of data and generate a signature for a plurality of fixed length overlapping windows of the stream of data. The device may select a predetermined number of the generated signatures for each Ln-byte segment of the data stream, wherein Ln is greater than a length of each of the windows. The network device may store the selected signatures in a bucketed hash table that includes a linked-list of entries for each bucket.Type: GrantFiled: June 17, 2008Date of Patent: June 14, 2011Assignee: Juniper Networks, Inc.Inventor: An-Cheng Huang
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Patent number: 7961122Abstract: A parallel based 5 bypass bin CABAC decoder may include a 3 bypass bins decoder appropriately coupled to a 2 bypass bins decoder. The 3 bypass bins decoder may have a first input receiving a bitstream, a second input receiving range values, a first output outputting a first bypass bin, a second output outputting a second bypass bin, a third output outputting a third bypass bin, and a fourth output outputting a shifted bitstream to the 2 bypass bins decoder. The 2 bypass bins decoder may have a first input to receive the shifted bitstream, a second input to receive the range values, a first output outputting a fourth bypass bin, and a second output outputting a fifth bypass bin.Type: GrantFiled: February 3, 2010Date of Patent: June 14, 2011Assignee: Himax Media Solutions, Inc.Inventor: Chien-Chang Lin
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Patent number: 7961132Abstract: In one embodiment, an A/D converter samples an analog input signal voltage by applying the input signal to a first capacitor terminal, while a second capacitor terminal is connected to ground via an NMOS sampling switch, to charge the capacitor to the input signal voltage. During an analog-to-digital conversion process, the second capacitor terminal may swing in a voltage range that extends below ground. A controller circuit provides bias voltage signals to a gate terminal and to a p-well of the NMOS sampling switch, to selectively turn the sampling switch on and off. In a first step of a multi-step sampling process, the controller very quickly discharges the gate terminal to ground to isolate a quantity of charge on the second capacitor plate. In a subsequent step of the sampling process, the controller circuit applies a negative voltage to the gate terminal and p-well to ensure that the quantity of change is substantially preserved during the ensuing analog-to-digital conversion process.Type: GrantFiled: February 3, 2010Date of Patent: June 14, 2011Assignee: Linear Technology CorporationInventors: Raymond T. Perry, Jesper Steensgaard-Madsen
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Patent number: 7956788Abstract: In an inventive photonic analog-to-digital signal converter (ADC), multiple opto-electric sampling devices are employed to successively sample an analog signal input. Optical clock signals having the same frequency but different clock phases are used, which are associated with the opto-electric sampling devices, respectively. Each sampling device takes samples of the analog signal input in response to the optical clock signal associated therewith. The resulting samples are processed to produce quantized samples. The inventive ADC outputs a digital signal representing the quantized samples.Type: GrantFiled: April 30, 2009Date of Patent: June 7, 2011Assignee: Alcatel-Lucent USA Inc.Inventors: Jaesik Lee, Young-Kai Chen
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Patent number: 7956787Abstract: A method for operating an N-bit SAR ADC as a greater than N-bit resolution SAR ADC includes the steps of taking a plurality of samples for each analog value being converted to a digital value by the SAR ADC. A portion of an LSB is added to all but one of the plurality of samples. The plurality of samples are then accumulated and output as a digital value. The digital value has a resolution greater than the N-bit resolution of the SAR ADC.Type: GrantFiled: December 19, 2008Date of Patent: June 7, 2011Assignee: Silicon Laboratories Inc.Inventors: Alan Westwick, Xiaoling Guo
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Patent number: 7956782Abstract: In general, this disclosure is directed to a differential current-mode sigma-delta digital-to-analog converter (SD DAC) with improved accuracy and reduced offset and gain errors. In one example, the SD DAC may include a current source configured to provide a differential current. The SD DAC may further include a switching network configured to adjust a polarity of the differential current according to a bit within the bit-stream to produce a differential current signal. The SD DAC may further include a current-to-voltage converter configured to convert the differential current signal to a differential voltage signal. In additional examples, the differential current source may include one or more source degeneration resistances. In further examples, the current-to-voltage converter may include a fully-differential operational amplifier. A low pass filter may be included within the current-to-voltage converter and/or coupled to the output of the current-to-voltage converter.Type: GrantFiled: June 11, 2009Date of Patent: June 7, 2011Assignee: Honeywell International Inc.Inventor: Paul M. Werking
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Patent number: 7952509Abstract: A successive approximation A/D conversion circuit for simultaneously sampling N channels of analog signals and for A/D converting the sampled analog signals, includes: N capacitive main DACs; a resistive sub DAC; N comparators; and a successive approximation control circuit, wherein the successive approximation control circuit determines high-order bit values of A/D conversion results of the N channels of analog signals by controlling the N capacitive main DACs and the N comparators, and determines low-order bit values of the A/D conversion results of the N channels of analog signals by controlling the resistive sub DAC and the N comparators.Type: GrantFiled: November 17, 2009Date of Patent: May 31, 2011Assignee: Fujitsu Semiconductor LimitedInventors: Kenta Aruga, Suguru Tachibana, Koji Okada
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Patent number: 7952499Abstract: Random access to run-length encoded data values is provided. A target value is identified by a logical index into a structure of run-length-encoded values. To access the value, a bookmark is selected based on the logical index, on a maximum logical index of the bookmark, and on a specified bookmark distance. An initial run in the structure is located, based on the selected bookmark. A final run is chosen, at most one bookmark distance from the initial run. The target value is the value of the final run. Efficiency heuristics are used when generating bookmarks or creating the structure of run-length-encoded values.Type: GrantFiled: January 29, 2010Date of Patent: May 31, 2011Assignee: Microsoft CorporationInventors: Bogdan Crivat, Cristian Petculescu, Amir Netz
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Patent number: 7952500Abstract: A method of encoding data structures using compressed object encodings during serialization. A compressed representation of the data is generated directly while encoding. Serialization means converting a data structure to a string of bytes for external storage or communication.Type: GrantFiled: January 27, 2009Date of Patent: May 31, 2011Assignee: Tatu Ylonen OyInventor: Tatu J Ylonen
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Patent number: 7948415Abstract: A DA converter includes a first DA conversion section for obtaining an analog output signal in accordance with a digital input signal value, and a second DA conversion section for obtaining an analog gain control output signal in accordance with a digital gain control input signal value. In the DA converter, the gain control of the analog output signal generated by the first DA conversion section is performed on the basis of the gain control output signal generated by the second DA conversion section.Type: GrantFiled: September 9, 2008Date of Patent: May 24, 2011Assignee: Sony CorporationInventors: Go Asayama, Noriyuki Fukushima, Yoshikazu Nitta, Yoshinori Muramatsu, Kiyotaka Amano
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Patent number: 7948409Abstract: A method for calibrating an initial driving signal for driving an optical pick-up head of an optical disk drive is provided. On one embodiment, said optical disk drive is utilized for reading or writing data on an optical disk, the optical disk comprises a plurality of auto power control areas (APC areas) and a plurality of data areas, and the APC areas and the data areas are interleaved in between. First, in the APC areas, an initial driving signal is used to drive the optical pick-up head to emit laserbeam. A detected level of the laserbeam is then obtained. An update initial driving signal is then calibrated according to the detected level and a target level.Type: GrantFiled: October 22, 2009Date of Patent: May 24, 2011Assignee: Mediatek Inc.Inventors: Gwo-Huei Wu, Kuo-Jung Lan, Yu-Hsuan Lin, You-Wen Chang
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Patent number: 7948414Abstract: A delta-sigma analog-to-digital conversion apparatus for receiving an analog input signal to generate a digital output signal includes a subtracting unit, a quantizer, and a feedback unit. The subtracting unit is utilized for performing a subtraction function to generate a subtracted signal according to the analog input signal and a feedback signal. The quantizer is coupled to the subtracting unit and utilized for performing quantization to generate a quantized signal according to the subtracted signal. The feedback unit is coupled between the subtracting unit and the quantizer, and utilized for providing the feedback signal to the subtracting unit according to the quantized signal. The subtracting unit is arranged to reduce signal input swing of the quantizer.Type: GrantFiled: August 9, 2009Date of Patent: May 24, 2011Assignee: Mediatek, Inc.Inventors: Tse-Chi Lin, Yu-Hsuan Tu, Chang-Shun Liu, Kang-Wei Hsueh
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Patent number: 7948417Abstract: A digital data harness, uses a signal specific conditioning circuit to interface with analog sensors. The signal specific conditioning circuits convert data signals from analog to digital and thereby allow the signals to be transmitted over a digital data harness.Type: GrantFiled: August 4, 2009Date of Patent: May 24, 2011Assignee: Hamilton Sundstrand CorporationInventors: Leo J. Veilleux, Jr., Peter J. Padykula
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Patent number: 7948422Abstract: The invention relates to a method for converting a voltage identification code includes the steps as follows. A special binary code range is obtained, and N special voltage identification codes corresponding to a special command are converted to N special binary codes under a converting relation, and the N special binary codes are used as the special binary code range. A first voltage identification code is converted to a corresponding first binary code under the converting relation. In addition, the first binary code and a first preset value are used to compute to obtain a second binary code, and the second binary code is not in the special binary code range.Type: GrantFiled: December 7, 2009Date of Patent: May 24, 2011Assignee: Asmedia Technology Inc.Inventor: Ming-Hui Chiu
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Patent number: 7932845Abstract: A self-calibrating analog-to-digital converter (ADC). The ADC includes multiple component ADCs to generate respective digital representations of an input signal in response to respective timing signals that are offset in phase from one another, each component ADC having a gain setting that controls a magnitude of the digital representations. The ADC further includes correction circuitry to generate a plurality of fast-Fourier transforms (FFTs) that correspond to the digital representations of the input signal and to adjust the gain settings of the component ADCs and/or phase angles of the timing signals based on gain and phase errors indicated by the FFTs.Type: GrantFiled: January 21, 2010Date of Patent: April 26, 2011Assignee: Telegent Systems, Inc.Inventors: Samuel Sheng, Weijie Yun
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Patent number: 7932843Abstract: A method of video decoding is provided that includes receiving a data stream comprising a sequence of syntax elements that were compressed using context-adaptive binary arithmetic coding (CABAC), such that the encoding of each bin of a bin string representative of a syntax element was performed by arithmetic encoding. Two consecutive bins of a syntax element are decoded in parallel. Speculative computation and prefetching is used to reduce the critical path and thereby improve processing speed.Type: GrantFiled: October 1, 2009Date of Patent: April 26, 2011Assignee: Texas Instruments IncorporatedInventors: Mehmet Umut Demircin, Vivienne Sze, Madhukar Budagavi
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Patent number: 7928878Abstract: An analog to digital converter includes a delta sigma modulator with a modified distributed feed-forward (DFF) topology. The modulator includes low pass filter circuitry that provides a first path to a first integrator and a second, feed-forward path to a second integrator that significantly reduce the out of band signal transfer function (STF) peaking of the modulator.Type: GrantFiled: September 30, 2009Date of Patent: April 19, 2011Assignee: Silicon Laboratories Inc.Inventors: Abdulkerim L. Coban, Alessandro Piovaccari
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Patent number: 7928883Abstract: Multiple digital signals from a single integrated circuit (IC) may be provided. The IC may receive an analog signal comprising a plurality of channels, convert the analog signal to a digital signal, and provide the digital signal to a plurality of digital channel tuners. The tuners may each select one of the plurality of channels and provide the selected channels as a plurality of digital output signals. A signal conditioner may be used to prepare the analog signal for digitization.Type: GrantFiled: March 13, 2009Date of Patent: April 19, 2011Assignee: Cisco Technology, Inc.Inventors: Neil C. Robertson, Jose M. Fernandez, Leo Montreuil